My objective is to read seven 512X512 float matrices from the SD card to the DDR memory (step accomplished already with each matrix occupying around 1Mb), then pass them from DDR to my custom IP block (I'm doing this transition with AXI DMA block), normalize them innside the custom IP block and then output them to DDR memory (also with the AXI DMA block).

Well, I'm doing my custom IP block in Vivado HLS and following the steps that I saw in this Xilinx manual (which shall be the ideal way to do this since its from Xilinx). It works for a 32x32 matrix.

But unfortunately, when increasing the matrix dimensions to 512x512, even doing only a multiplication by 2.0 of each matrix' parameter, the BRAM_18K utilization is 365%!!

What can I do do brutaly decrease the % of resources used? I'll need to do lots of operations to the matrices inside the custom IP block and if a simple multiplication by 2.0 uses 365% of BRAMs a solution that decreases the amount of this example to 80/90% is not good enough. What I'm looking for is a solution that sets the BRAM utilization to around 5% in this example.

  • \$\begingroup\$ 512x512x4 = a megabyte of matrix. How many 18K block rams do you have? You'll almost certainly have to do it in sub-matrixes like BLAS does. \$\endgroup\$
    – pjc50
    Jun 3 '15 at 15:33
  • \$\begingroup\$ 280 18K BRAM blocks. BLAS? \$\endgroup\$ Jun 3 '15 at 17:16
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    \$\begingroup\$ en.wikipedia.org/wiki/Basic_Linear_Algebra_Subprograms ; implementations usually subdivide matrices into tiles to fit in vector processors. \$\endgroup\$
    – pjc50
    Jun 3 '15 at 19:26
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    \$\begingroup\$ I'm doing a big matrix multiplication on an FPGA. In fact, it's much bigger than yours - something like 75000x75000. It's only tractable because of several levels of algorithmic optimisation before I get anywhere near the hardware. Which is the core of the question, what properties of the matrix, if any, can you exploit? \$\endgroup\$ Jun 11 '15 at 14:56
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    \$\begingroup\$ Well have you measured your throughput on a CPU for comparison? Memory bandwidth is a serious consideration, so you want to minimise the number of times you have to copy any part to the FPGA - if you can do it once so much the better, or split it between CPU and FPGA or some other combo. Your question is so open ended that its basically impossible to answer as is. Good luck with it! \$\endgroup\$ Jun 12 '15 at 11:55

My guess is that there isn't enough space in block RAM to store everything. You're going to have to find a way to work on it in smaller pieces that will fit in block RAM.

  • \$\begingroup\$ I'm really surprised by this. I thought that the FPGA side of a Zedboard had way more space. So the way is to divide my 512x512 matrices into smaller pieces or do you haved another suggestion? \$\endgroup\$ Jun 4 '15 at 10:00
  • \$\begingroup\$ Yeah, you're going to have to either do some sort of divide and conquer approach to re-use resources in time or get a bigger FPGA. \$\endgroup\$ Jun 5 '15 at 5:41
  • \$\begingroup\$ And with that divide and conquer strategy, by your experience do you think I will be able to still significantly reduce the running time when comparing to software? \$\endgroup\$ Jun 5 '15 at 10:24
  • \$\begingroup\$ It suspect it depends on the structure (or not) of your matrix. Does it have any nice properties that make it amenable to faster strategies? Is it a changing matrix? So many questions... \$\endgroup\$ Jun 11 '15 at 14:54
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    \$\begingroup\$ I answered in your other response. If you manage to make an answer with some good tips (that you used in your 75000x75000 matrices) I will gladly mark it as a solution \$\endgroup\$ Jun 11 '15 at 15:09

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