I am making a testbench in Verilog where it will call different test cases from different modules, each module, one test case/task. I am a beginner in making testbench, can I know where should I instantiate the DUT object? In the testbench file or in the task?


The DUT module should be instantiated in the testbench module file. Modules can't be instantiated in a Verilog task.

See also: Can anyone help me to create a Verilog testbench?

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    \$\begingroup\$ wow, thank you very much. you saved me a lot of time figuring what to do. never thought it will be answered in one day. thanks again. \$\endgroup\$ – Dragonald Valenciano Jun 5 '15 at 0:27
  • \$\begingroup\$ another question: can task have no inputs? or it should be at least one? \$\endgroup\$ – Dragonald Valenciano Jun 5 '15 at 0:29
  • \$\begingroup\$ You're welcome. A task does not need any inputs. Take a look at the free IEEE Std 1800-2012 (google it). \$\endgroup\$ – toolic Jun 5 '15 at 0:30

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