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I am making a testbench in Verilog where it will call different test cases from different modules, each module, one test case/task. I am a beginner in making testbench, can I know where should I instantiate the DUT object? In the testbench file or in the task?

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The DUT module should be instantiated in the testbench module file. Modules can't be instantiated in a Verilog task.

See also: Can anyone help me to create a Verilog testbench?

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