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I have a question about power sequencing requested by FPGA/MCU datasheets. I always see in datasheets that a particular power supply input must reach a voltage level before another power supply input (for example Vcore before Vio). But every time I look at evaluation boards I can't find anything that does that (e.g. power sequencer ICs). My question is related to FPGAs and MCUs, and not to particular ICs that maybe must have a described power seq. to correctly work.

Since my evaluation boards never fault as power up, is this power sequencing really necessary? Or is it perhaps accomplished in some way by the decoupling capacitors?

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  • \$\begingroup\$ they are necessary and probably accomplished in not so evident ways, the latter being true only for reliable manufacturers. if you don't respect the power sequence you can possibly damage the chip, that does not seem a nice scenario for an evaluation board. \$\endgroup\$
    – Vladimir Cravero
    Commented Jun 5, 2015 at 8:24
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    \$\begingroup\$ It's entirely possible the boards you're looking at meet the requirements simply by virtue of how they're set up. If the 1.8v rail is derived from the 3.3v rail, it's never going to power up before it. \$\endgroup\$
    – Nick Johnson
    Commented Jun 5, 2015 at 8:29
  • \$\begingroup\$ Always obey the rules about Power Seq. in datasheets. One possible consequence of breaking proper order may be Latch-Up. \$\endgroup\$
    – Al Bundy
    Commented Jun 5, 2015 at 8:40
  • \$\begingroup\$ @Yaro, we could look at design details of the development boards which you have encountered. Could you post the links to the dev boards, please? \$\endgroup\$
    – Nick Alexeev
    Commented May 1, 2019 at 22:56
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    \$\begingroup\$ What kind of evaluation boards are you looking at? I see power sequencing on pretty much every FPGA board I look at. Sometimes it's not obvious though. If you see things like supervisors, load switches, regulators with enable lines running off to somewhere, or sequencers (obviously). Sometimes it's a CPLD. Simple MCUs don't have too much of this, but the more complicated a processor is, and the more supplies it has the more likely you will see power sequencing. \$\endgroup\$
    – DKNguyen
    Commented May 2, 2019 at 4:40

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Each evaluation board must have the right power stage ready to power sequentially each of the voltage needed for the FPGA or MCU.

You can take a look in the schematics of your EVBoard (usually available in manufacturer website). The power stage of your EVBoard should have some DC/DC converters (or lineal regulators) each of them with a EN pin (or another similar behaviour name).

With these pins could be defined a chained power-up strategy. Asserting each with a previous powered voltage in the order established at the datasheet.

Also, it's possible use a voltage supervisor chip that assert the EN pins in a defined way.

A more analogical way is use a RC circuit to time the assertion of EN pin.

In conclusion, don't worry about the power sequence of your EVBoard, it has been correctly designed by manufacturer. You must take it into account in your own FPGA or MCU pcb design.

Best regards

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