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schematic

simulate this circuit – Schematic created using CircuitLab

Using a rc network to smooth a PWM signal from a microcontroller, to a true analogue voltage.

What will be the effect of having the resistor on the source (microcontroller) side of the capacitor vs the load side?

What would be the effect of having the resistor in series with the capacitor but parallel to the load and source?

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  • \$\begingroup\$ In both cases it's not an effective RC filter any more. \$\endgroup\$
    – pjc50
    Commented Jun 5, 2015 at 15:11
  • \$\begingroup\$ What you have drawn in your edit is a sort of ESR-increase. Verify that the load is still connected to the signal directly, but the capacitor is only hindered more in compensation. Assuming the signal source doesn't supply a high current as well, then you won't filter at all. Also, you MCU doesn't create a sine (A sine source goes negative and positive), but the intention is clear. Would you like me to extend my answer to also address your drawing, explaining why this doesn't really help any at all? \$\endgroup\$
    – Asmyldof
    Commented Jun 5, 2015 at 16:48
  • \$\begingroup\$ if you could extend it that would be appreciated, in reality id be producing a square wave, im not sure at what frequency, and the resistor and capacitor values ive chosen have been plucked from the air \$\endgroup\$
    – Ben
    Commented Jun 5, 2015 at 17:19

4 Answers 4

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To get a good understanding of all that goes on here, you really need to draw. Maybe some issues might be clearer just by the picture:

schematic

simulate this circuit – Schematic created using CircuitLab

To handle the last one first:

In this case, you are just increasing the load to the capacitor, so that's not very useful in most cases (there are exceptions, but in general, why would you increase the drain?)

In the second drawing the signal source can supply a fixed amount of current, or drain it away. Often with MCUs the current it can supply or drain is enough to make a very large ripple on the capacitor of 1uF. So in this case, you are not really limiting the ripple current, but you are limiting the amount of power the LOAD can take out the capacitor. So you would need a quite large capacitor, and most MCUs don't really like that.

The first is the best solution, especially if your LOAD is very light, in fact, lighter than I drew it. The R and C will limit the current the MCU can supply into the capacitor and take out of it. This means that the voltage on the capacitor will go up and down much more slowly than without the resistor. So, if the frequency is high enough, you will not see much ripple at all.

But I did take an equivalent LOAD of 250 Ohm on purpose, because you can see, that if your LOAD is quite heavy, this solution will give your device much less power. Now, because an MCU can't supply too much current and doesn't really like really large capacitors on its output, it's better to make the LOAD light and the R and C small. So if you want to drive something heavy, it's better to amplify the signal (with an Audio Op-Amp, for example, if your resulting/filtered analogue signal isn't too high frequency.)

But if you want to use it in a light LOAD, such as an op-amp or something else with more than 100kOhm input impedance, you can very easily create a smooth signal from an MCU PWM with components like these:

schematic

simulate this circuit

The RC-time of the components is high enough for most of the PWM range in 10kHz (if you expect a lot of 0% to 2%, you might need to increase the resistor a bit), but doesn't annoy your MCU too much. The 1M LOAD doesn't really do enough to mention, but higher is better. If that LOAD is the input to a normal Op-Amp such as the LM358 types, you can easily ignore its effect.

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  • \$\begingroup\$ My question wasn't quite clear enough, i agree a drawing would be very handy however I'm on my phone. \$\endgroup\$
    – Ben
    Commented Jun 5, 2015 at 16:05
  • \$\begingroup\$ @Ben My point wasn't intended as "jeez! you need to make an image before we answer", I meant at the least: "If you draw for yourself your options, you might see some of what confuses you", such as the third option just increasing the resistive LOAD to the C and MCU. So I made the drawing for you, and quite happy to, I'm starting to get handy with it again. \$\endgroup\$
    – Asmyldof
    Commented Jun 5, 2015 at 16:10
  • \$\begingroup\$ my comment was un finished, i intended to say that the third scenario should have the resistor placed on the same "leg" of the circuit as the capacitor in series with it. I am driving a the analogue voltage into a high impedance input of another MCU. \$\endgroup\$
    – Ben
    Commented Jun 5, 2015 at 16:17
  • \$\begingroup\$ Thank you very much for your effort, it is much appreciated. \$\endgroup\$
    – Ben
    Commented Jun 5, 2015 at 16:18
  • \$\begingroup\$ @Ben It's why we're here. Congratulations on Ben still being available by the way. \$\endgroup\$
    – Asmyldof
    Commented Jun 5, 2015 at 16:30
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You want the capacitor after the resistor.

The other way is really not a low pass filter if you think of the digital output as being s voltage source. Of course it's not, so some filtering will happen anyway, but there are two problems with that. First, it will heavily load the digital output at edges, exceeding the allowed source/sink current. Second, the filtering that does happen is proportional to the impedance of the digital output, which is poorly specified, if at all. Don't do it.

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If the resistor is in series with the capacitor after it (in parallel with the load) the current to charge the capacitor must flow through the resistor and the capacitor charging necessarily takes time. If the load is essentially an infinite or a very high resistance eg the input of an opamp or similar, then the capacitor charges exponentially. Even if the input source was ideal with zero impedance the resistor would control the charging rate.

If the capacitor is placed from input to ground a following resistor has no effect on its charge or discharge rates. There is no filtering effect. See here and here. If the input was ideal with zero impedance it would 'try' to charge the capacitor in zero time with infinite current. If you were using an ideal capacitor as well 'the results would be "unpleasant".

Left: R controls charge/discharge current
Right: Current potentially "infinite"

enter image description here

If you place the resistor and capacitor in series you get a Zobel network and here. This has applications in some circumstances but is not useful for PWM smoothing. (At DC the impedance is infinite and it decreases with increasing frequency).

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  • \$\begingroup\$ If the load is essentially an infinite or a very high resistance eg the input of an opamp or similar, then the capacitor charges exponentially. Even if the input source was ideal with zero impedance the resistor would control the charging rate. I don't like this statement. The capacitor will always charge exponentially, and the resistor will always control the charging rate. It's better to say that any load taking more than a small fraction of the peak charge current will affect the charge time. \$\endgroup\$
    – Matt Young
    Commented Jun 5, 2015 at 15:39
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If you put the capacitor across the input PWM then it will not filter very effectively (assuming a CMOS push-pull output drive) and the output voltage may not be accurate because the charge and discharge currents will be determined by the Idss of the p-channel and n-channel MOSFETs in the driver. It will be quite nonlinear (this is important!). It will draw excessive current spikes from the power supply, causing EMI. It will cause excessive power dissipation (perhaps >100mW) and virtually all that will be dissipated in the chip. To get a similar 'time constant' to an R/C with 10K and 100nF you'd need a 10uF capacitor.

A resistor across the load will take the above situation and make it a bit worse (or a lot worse depending on how low the resistor value is compared to the output current capability of the CMOS output.

Below (bottom set of traces) is a plot of a 10K/100nF filter (red trace) compared to a 74HC00 output driving a 10uF capacitor (violet trace), both at 10kHz with 10% duty cycle. As you can see, there is a lot of error in the 74HC00 version.

enter image description here

This is a direct result of overloading the nonlinear CMOS output stage- the n-channel MOSFET has a higher Idss so it dominates and the error exceeds 50%.

The green trace at the top is the 10K/100nF filter followed (without buffering) by 20K series and another 100nF to ground. As you can see the noise is greatly reduced (less than half a mV at 500mV).

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