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Although Schmitt triggers are not usually regarded as latches with setup/hold constraints, a Schmitt trigger is functionally a sort of latch which is forced one way when the input is above a certain threshold, forced the other way when the input is below a certain threshold, and is expected to hold its value when the input is between the upper and lower thresholds. While the thresholds may or may not be specified in such fashion as to have a non-overlapping region between them, the fact that a device doesn't switch at a particular voltage but switches at a voltage near that would imply that the former voltage should be within the "hold" zone. For example, given http://www.ti.com/lit/ds/symlink/sn74ahct14.pdf

Table 7.5 Electrical Characteristics ![enter image description here][1]

which guarantees 0.4V hysteresis, if device outputs high while the input sits at 1.2 volts, then goes low when the input rises to 1.3 volts and sits there awhile, it must remain low until the input goes below 0.9 volts. If the output hadn't gone low until the input rose to 1.5 volts, it could go back high as soon as the input went back down to 1.1 volts.

Because the Schmitt trigger is a latching device, it will necessarily be, like all latching devices, susceptible to being placed in a metastable condition. While an ideal Schmitt trigger would switch exactly once if given a signal which never deviates by more than +/- 0.2V (half the hysteresis voltage) from a monotonically rising or falling waveform, it must like any latch have input conditions which would induce metastability. Most latches and latching devices have designated setup/hold timings and promise that they will not go metastable unless those timings are violated. Do Schmitt triggers offer any guarantees, e.g. promising that a signal that crosses the upper threshold for less than some maximum "reject" time will not cause the output to switch at all, and any signal which crosses the threshold for more than some "capture" time will be guaranteed to cause the output to switch and stay switched? Are such guarantees documented anywhere?

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Such considerations simply don't apply to the normal applications of Schmitt triggers. Schmitts are generally used where the input slew rate is much less than the output slew rate. With a slow input, the trigger point is not clearly defined, being affected by other factors such as noise and feedback from the switching transients as the output changes. Once the trigger point is reached, the positive feedback pulls the threshold quickly to the other level, and oscillation is prevented.

However, it is entirely true that Schmitt triggers exhibit metastability, and this was demonstrated in 1977/1979 by a series of remarks in the IEEE Transactions on Computing, by E.G.Wormald and Thomas Chaney. See http://fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm for a discussion of the subject.

So basically, Schmitt triggers are not much use for fast signals. For slow signals, they are very effective, but in these cases the low frequencies make metastability much less of a problem, since high sampling rates don't make sense, and there is relatively more time for metastable conditions to resolve themselves.

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  • \$\begingroup\$ Schmitt triggers are often used on signals which drive actions without being sampled by or synchronized to any other clock. If an optical sensor is driving a counter, metastability which causes the counter to receive a signal whose high and low times don't match the counter's requirements may cause the count to be corrupted. Is there any way to quantify such dangers beyond "hope for the best"? \$\endgroup\$ – supercat Jun 5 '15 at 20:10
  • \$\begingroup\$ Metastabilty parameters have been characterized for many logic families, but always in terms of setup/hold times. In your case the pertinent factor is behavior of the single input around the threshold. You would have to do your own characterization, specifying slew rate, SNR and noise spectral density, along with open-loop gain and response time of the comparator you're using. Why the concern? \$\endgroup\$ – WhatRoughBeast Jun 5 '15 at 21:03
  • \$\begingroup\$ When practical, I prefer to use devices in ways that are specified to work, rather than ways which happen to work with today's batch of parts but might not work given tomorrow's. In practice I suspect that the probability of Schmitt trigger metastability is extremely tiny relative to other possible causes of circuit malfunction, but it would be nice to have some documentation sufficient to either determine that the risk is acceptably small, or identify something cheap that can be done to ensure that the risk will be acceptably small. \$\endgroup\$ – supercat Jun 5 '15 at 21:13
  • \$\begingroup\$ Personally, I suspect the most robust approach would be to have flops with separate clock inputs for the master/slave latches, and measure setup times from when the first input goes high and propagation times from when the second goes high. Provided any runt pulses on either input were preceded or followed by valid pulses on that input without any intervening transitions on the other, such pulses could not cause metastability problems. If a noisy signal were passed through gates with different switching thresholds before being passed to the two clock inputs... \$\endgroup\$ – supercat Jun 5 '15 at 21:42
  • \$\begingroup\$ ...then provided that any time the signal reached the point where it could be considered high, it would continue to the point of definitely being high before going low, and vice versa, any output metastability caused by a slowly-rising clock signal would be resolved before the output was sampled by the next stage. I can't think of any recent devices that use such dual-phase clocking, however. \$\endgroup\$ – supercat Jun 5 '15 at 21:45

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