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I have a JTAG bus that I need to go over PCB (or could make cable) for about 12 inches. I am trying to figure out the signal integrity specs for the JTAG bus ... what trace width vs. trace length I can use and how much dB loss per unit length?

Trying to understand how long traces can be.

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  • \$\begingroup\$ Programming Altera PLDs with JTAG didn't work further than about 250mm on a job that I did and getting Altera to cough up the facts was a nightmare. That was about 5 years ago btw. Basic signal reflections was the problem. I never investigated it further because it wasn't an important product feature but I suspect some form of termination could be made to work. \$\endgroup\$ – Andy aka Jun 5 '15 at 21:50
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I would not be worried about loss, because you are not transmitting any power. For a simple implementation, the trace length will dictate the signal propagation time on the bus, and therefore the maximum frequency you can run the bus at.

The trace impedance is also not critical: As long as you maintain the impedance consistently, you will be able to deal with reflections. If you only connect a single JTAG target, you can get away with series termination of your signals. For a typical 50Ω impedance trace, add a ~30Ω resistor in series with the driving pin (close to the JTAG adapter for TDI, TMS, and TCK; close to the JTAG TAP for TDO). Of course the exact numbers depend on the ICs you are using and their driving abilities.

The longer your signal traces are, the more capacitance they will present to the driving buffer. A higher capacitance will reduce the maximum speed you can attain over the link.

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    \$\begingroup\$ Three comments: 1) you can still have loss even if you are not "transmitting power". Try running a 10 GHz signal through that path and you will see loss. Below ~5GBps not something to worry about at all. 2) It will be vise to match the PCB trace impedance to the cable impedance, or you may get reflections. 50R is not a bad number to use. More important will be to avoid longer stubs. 3) Longer traces will not limit the maximum speed. Read and understand transmission lines. - Other then that, good answer. \$\endgroup\$ – Rolf Ostergaard Jun 6 '15 at 6:47
  • \$\begingroup\$ Could you please elaborate on why in this specific case longer traces will not limit the maximum speed? For a simple synchronous JTAG implementation, I see a limit because of finite roundtrip time between TCK going out, and TDO coming back. \$\endgroup\$ – corecode Jun 6 '15 at 9:53
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    \$\begingroup\$ The answer talked about capacitance being the thing limiting speed. That's not the case. You may have a scenario where the setup/hold times of your JTAG driver is arranged so that it only works at full speed with shorter trace lengths for timing reasons (have never experienced that, but who knows). \$\endgroup\$ – Rolf Ostergaard Jun 6 '15 at 12:32
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    \$\begingroup\$ Within realistic limits the longer trace will just represent a longer delay. And higher capacitance. But that comes with more inductance as well, thus forming a mostly loss-less transmission line. Not impacting rise/fall times much. So capacitance is not a reason to limit trace length. \$\endgroup\$ – Rolf Ostergaard Jun 6 '15 at 12:41

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