# Map error in ISE caused by PLL

I'm working on a design using a Spartan6 FPGA, I recently made a change that added a PLL to the design to allow for faster clock speeds, however this caused a problem during the "map" command:

    The following 1 components are required to be placed in a specific relative placement form.
The required relative coordinates in the RPM grid (that can be seen in the FPGA Editor)
are shown in brackets next to the component names. Due to placement constraints it is impossible
to place the components in the required form.



What would cause PLL_ADV to be locked to this specific location (which I assume is being occupied by a different PLL), when there are three other possible locations for it. I have made no changes to the default configuration of the PLL element

This error is related to the RPM grid mentioned in the error message. Next a definition of RPM grid from a Xilinx Link

A Relationally Placed Macro (RPM) defines the spatial relationship of the primitives that constitute its logic. An indivisible block of logic elements that are placed as a unit into a design.

That is, the PLL you have added have her position in the FPGA relatively related to other logic. Mapper have tried to place it but it have failed due to design constraint or maybe because there is more PLLs that need the place of the RMP PLL.