I'm working on a design using a Spartan6 FPGA, I recently made a change that added a PLL to the design to allow for faster clock speeds, however this caused a problem during the "map" command:

    The following 1 components are required to be placed in a specific relative placement form. 
    The required relative coordinates in the RPM grid (that can be seen in the FPGA Editor) 
    are shown in brackets next to the component names. Due to placement constraints it is impossible 
    to place the components in the required form.

    PLL XLXI_52/PLL_ADV (0, 0)               locked to site PLL_ADV_X0Y0

What would cause PLL_ADV to be locked to this specific location (which I assume is being occupied by a different PLL), when there are three other possible locations for it. I have made no changes to the default configuration of the PLL element


This error is related to the RPM grid mentioned in the error message. Next a definition of RPM grid from a Xilinx Link

A Relationally Placed Macro (RPM) defines the spatial relationship of the primitives that constitute its logic. An indivisible block of logic elements that are placed as a unit into a design.

That is, the PLL you have added have her position in the FPGA relatively related to other logic. Mapper have tried to place it but it have failed due to design constraint or maybe because there is more PLLs that need the place of the RMP PLL.

Said that, what can you do about this issue? Some examples:

  • Disable the RPM grid of the core if possible. Some times can be disabled, but in other cases the RPM grid is needed for the core to work.
  • Lock the place of the RPM PLL with a placement constraint. Maybe the rest of the core could be placed in the RPM grid locations
  • Lock the place of the PLL that occupy the place demanded by the RMP PLL
  • Consider use a DCM instead a PLL. More numerous and less power consumers.
  • Others strategies.

In conclusion, help to the mapper with some instructions.

Best regards

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