The part under question is PCM1808. This device needs an external system clock on the SCKI pin. From the master device it shall need LRCK, BCK & DOUT. The LRCK chooses the left/right channels. BCK is the clock signal sent into the ADC to drive the DOUT bits out. The component has 24 bits resolution.

Now assume that I have a 16.384 MHz crystal. According to Table 1, this could mean sampling frequency of 32KHz or 64KHz. The datasheet says that "The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode.". I am lost, how does the device know if I want it to sample at 32KHz or 64KHz, automatically!? This appears ambiguous to me, almost like magic.

Then, does the master device need to read the ADC continuously? I mean, there will be times when reading samples will not be needed. What happens if I am not reading the ADC at all? Do I need to send some command to make it sleep and wake up?

The master device is fed by the same 16.384MHz clock. However, obviously it does not send out the BCK signal at the same rate of 16.384MHz. If one is using I2S data format, at what rate does the master device read the ADC to get all the samples by sending out BCK and reading data on DOUT and how is this ensured? Is it by using timer interrupts or special built-in hardware for I2S data transfers?

  • 2
    \$\begingroup\$ With I2S, the master controls the sample rate by controlling the bit clock. The number of bits per word, and number of channels is either fixed, or pre-programmed by master. en.wikipedia.org/wiki/I%C2%B2S \$\endgroup\$
    – user57037
    Commented Jun 8, 2015 at 1:23
  • \$\begingroup\$ Consider the ratio between LRCK and the sample rate. \$\endgroup\$
    – CL.
    Commented Jun 8, 2015 at 6:44
  • \$\begingroup\$ This may be helpful in understanding I2S as well. Its a question I had a while back: electronics.stackexchange.com/questions/102588/… \$\endgroup\$
    – Funkyguy
    Commented Aug 19, 2015 at 16:39

1 Answer 1


If you look at Table 2, you'll see that the MD0 and MD1 pins control how the master utilizes the clock input (either 256, 384, or 512 * fs). Once you select one of these options, you can use your crystal frequency to tell you the sampling frequency.

Once you know the sampling frequency, you can use the resolution to give you the BCK rate. This particular part has 24-bit resolution. Each "frame" of audio consists of two channels, left and right. Each channel has a 24-bit value. Therefore, each sample is 24-bits of data. If, for example, you are using 64KHz sampling rate (by selecting 256fs using MD0 and MD1 pins), then you can get the BCK rate:

24 bits/sample * 64,000 samples/sec = 1,536,000 bits/sec

Therefore, your BCK frequency is 1.536 MHz. Your L/R clock will be 24 times slower than this, since it oscillates when the channel switches, which is every 24 bits.


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