The part under question is PCM1808. This device needs an external system clock on the SCKI pin. From the master device it shall need LRCK, BCK & DOUT. The LRCK chooses the left/right channels. BCK is the clock signal sent into the ADC to drive the DOUT bits out. The component has 24 bits resolution.
Now assume that I have a 16.384 MHz crystal. According to Table 1, this could mean sampling frequency of 32KHz or 64KHz. The datasheet says that "The PCM1808 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode.". I am lost, how does the device know if I want it to sample at 32KHz or 64KHz, automatically!? This appears ambiguous to me, almost like magic.
Then, does the master device need to read the ADC continuously? I mean, there will be times when reading samples will not be needed. What happens if I am not reading the ADC at all? Do I need to send some command to make it sleep and wake up?
The master device is fed by the same 16.384MHz clock. However, obviously it does not send out the BCK signal at the same rate of 16.384MHz. If one is using I2S data format, at what rate does the master device read the ADC to get all the samples by sending out BCK and reading data on DOUT and how is this ensured? Is it by using timer interrupts or special built-in hardware for I2S data transfers?