3
\$\begingroup\$

I'm thinking of making an 8MHz about-square clock starting from a 24MHz about-square clock. All signals are CMOS with 3.3V(±10%) power.

What are my options? I'd like it low-power, cheap and easy to source, compact.

Note: the divide-by-N 74HC4059 does not match my "8 MHz about-square clock" requirement; the output duty cycle is about 1/3.

Update: I located that On Semi application note trying to do what I want, except that's using a lot of circuitry more ICs than in my dreams. I wish that divide-by-3 function existed pre-integrated... AND8001-D figure 2

Update following comment about the lack of symmetry requirement: the available 24MHz at input has tlo>16.5ns, thi>16.5ns, and negligible jitter. The output signal should have tlo>50ns, thi>50ns, and no long-term drift. Thus if my math is right, in the above circuit I have to keep the difference of delay between (rising-input-edge to rising-output-edge) and (falling-input-edge to falling-output-edge) within ±8ns (with 166ps engineering margin).

\$\endgroup\$
  • \$\begingroup\$ Standard logic being only fundamental digital gates (AND, OR, NOT) ? Because you can get divide by N ICs already to go or you can get up a counter with some discrete logic on the side. \$\endgroup\$ – efox29 Jun 8 '15 at 6:20
  • \$\begingroup\$ EXOR and divide by 4 = slightly asymmetrical divide-by-3. \$\endgroup\$ – Andy aka Jun 8 '15 at 7:48
  • 1
    \$\begingroup\$ I think what is in the On Semi app. note is about as little circuitry as possible for a "neat" solution. A different approach would be to first make the 1/3 dutycycle signal and then "fix" that to be 1/2 duty cycle but you'd end up with at least as much components. \$\endgroup\$ – Bimpelrekkie Jun 8 '15 at 8:31
  • 1
    \$\begingroup\$ I've undeleted my answer, and modified it to incorporate the suggestion you made in your comment. Even with the additional part, I think its still a good way to accomplish this with a guaranteed 50-50 duty cycle. \$\endgroup\$ – tcrosley Jun 8 '15 at 18:45
  • 1
    \$\begingroup\$ The 74HC4059 at 3.3v has an fMAX right around 24MHz and certainly will fail with temperature changes. A 74HC00 has a max transition and propagation of ~50nS at 3.3v. Given that the entire period of a 24MHz cycle is 41.667nS, that isn't going to work either. You'll have to increase your supply voltage or look at a faster family of IC's, perhaps such as the AHC series. \$\endgroup\$ – rdtsc Jun 8 '15 at 19:29
6
\$\begingroup\$

You can implement the ON Semi circuit with only three small packages. Two 74HC74 dual D flip-flops and a 74HC02 quad 2-in NOR gate. There's a FF left over so you could also get 4MHz or 12MHz simultaneously.

Recall that an AND gate is the same as a NOR with each input inverted, so just use the Q outputs rather than the /Q outputs for the AND gate.

You might be able to further reduce it to two packages using a 4-bit synchronous counter but I doubt you'll get much lower in BOM cost (42 cents US in 100's at Digikey for the three)

\$\endgroup\$
  • \$\begingroup\$ Good point about being able to use either the Q or /Q outputs as needed to avoid inverters. \$\endgroup\$ – tcrosley Jun 8 '15 at 12:57
  • \$\begingroup\$ Yes. One issue is that I need to invert the clock for (at least one of) the D gates, and the associated delay will contribute to imbalance of the output. If only we had negative-going-clock D-gate; or perhaps using a JK flip-flop? \$\endgroup\$ – fgrieu Jun 8 '15 at 13:21
  • \$\begingroup\$ The propagation delay of the right-hand flip-flop also contributes to imbalance. If you really need close to exact 50% duty cycle you should use Olin's PLL method and follow it up by a flip-flop to get 50%. You'll still get some jitter, of course. There are clock synthesizer ICs that integrate some of this, but most are aimed at higher frequencies and very high performance. \$\endgroup\$ – Spehro Pefhany Jun 8 '15 at 13:47
1
\$\begingroup\$

Use a PLL (phase locked loop) to multiply the original frequency by 2. This allows dividing by 3 that doesn't need to be square, then followed by a divide by 2 to yield a square output.

\$\endgroup\$
  • \$\begingroup\$ Is this going to be simpler/cheaper/smaller than the circuit from On Semi posted in the question? \$\endgroup\$ – tcrosley Jun 8 '15 at 11:53
  • 1
    \$\begingroup\$ I have no idea since that's for the OP to determine. I generally don't follow links in questions, unless it's a datasheet about a part being directly asked about. It's not my homework to do. I'm just giving the OP a general idea. \$\endgroup\$ – Olin Lathrop Jun 8 '15 at 11:55
  • \$\begingroup\$ The OP posted the circuit from On Semi (three FF's plus some glue logic) in the question. You didn't have to follow a link. Anyhow the OP thought that was too much circuitry. I wish him luck. \$\endgroup\$ – tcrosley Jun 8 '15 at 12:02
  • 1
    \$\begingroup\$ Look again -- actually the output is square -- the on period is 1.5 cycles of the 24 MHz clock, and off period is also 1.5 cycles. It has to be a alternating rising/falling edge because of dividing by a odd number. Note the rising edge of the output always lines up with a rising edge of the input. \$\endgroup\$ – tcrosley Jun 8 '15 at 12:49
  • 1
    \$\begingroup\$ @SpehroPefhany The OP's requirement is "8 MHz about-square clock", unclear what that really means and whether the circuit posted in the question is close enough. \$\endgroup\$ – tcrosley Jun 8 '15 at 16:12
1
\$\begingroup\$

As a derivation of tcrosley's answer, the PIC18F2550 (24Pin SOIC or DIP) has a nice PLL block. This can take a 24MHz input, prescale it by a factor of 12 down to 4MHz (PLLDIV=111), feed that into a PLL which will step it up to 96MHz, then feed that through a postscaler with a factor of 6 (CPUDIV=11) to make 16MHz.

This can then feed the Timer1 module which can be configured to toggle a CCP pin on compare match and reset the timer - you set the compare value as zero which means every clock cycle a match will occur and the CCP pin will toggle thus producing a 50% duty cycle 8MHz signal (I know this works in AVRs, so I am assuming it will also work in PICs).

A bit contrived, but it is a single chip approach. Plus it means you have a PIC running at 16MHz to use for other things.


EDIT:

As an alternative, you can use postscaler factor of 3 (CPUDIV=01) giving a 32MHz system clock. Then you will automatically get FCPU/4 from the CLKO pin (RA6) which should be 8MHz 50% duty cycle. Plus then you have a nice PIC running at 32MHz internally to do anything else you might need.

\$\endgroup\$
  • 2
    \$\begingroup\$ Thanks for the comment re instruction timing on my approach. You're quite right. I looked at the PIC18 but was trying to avoid it because of the cost. Nice answer BTW. \$\endgroup\$ – tcrosley Jun 9 '15 at 0:40
  • 1
    \$\begingroup\$ There's this pesky note on page marked 387: " When 2.0V < VDD < 3.3V, the maximum crystal frequency = (16.36 MHz/V)(VDD – 2.0V) + 4 MHz. "; which I read as limiting input frequency to slightly less than 20MHz at the lower limit of my 3.3V(±10%) power supply range. Also, the power consumption is non-trivial. \$\endgroup\$ – fgrieu Jun 9 '15 at 4:43

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.