Syncronization Flip-flops

Question

I've a doubt about clock domains and synchronization FF. I'm working on a FPGA and I've two clock domains. In the firs clock domain there is a clock frequency of 125 MHz, in the second the frequency is generated by a PLL that has in input the 125Mhz and it generates a 12.5 MHz.

Are syncronization FFs, between the clock domains, needed for signals that goes from one domain to the other ? I know that when the signals are asyncronous or unrelated I must put syncronization FFs, but in this case the frequencies are related. Is it safe to eliminate the FFs ?

Thanks

Answer 1

Since you use a PLL to generate your 12.5MHz clock, the phase relationship will be kept by the synthesis tool, whatever it is. This means the timing analysis will properly report any path between the two clocks and will tell you if it can't satisfy the setup/hold relationship. The clocks will also likely be edge-aligned, but this depends on the PLL's configuration.

It is easy to perform a clock-domain transfer between an edge-aligned 12.5MHz to 125MHz. If the source setup within 8ns, the 125MHz will latch the value without problem. The other direction is also easy, except you must keep any value for 10 125MHz clock-cycles to make sure the slower clock latch the new value (the tool won't verify this).

It is sometimes preferable to consider the two clocks asynchronous. An example case would be if the clock ratio is 11/13, it may be impossible to satisfy timings between the clocks. In that case, just consider them asynchronous, put false path constraints and use FIFOs, synchronization registers or any other technique to transfer data.

In your case, consider them synchronous, it shouldn't be difficult to meet timings if they are edge-aligned or if their phase relationship isn't utterly bad. Also be sure to verify the timings report, if the cross-domain paths aren't there, then you know there is something wrong.

Answer 2

This is going to depend on the delay which the PLL produces. If the PLL produces zero delay, that is, a 12.5 MHz clock edge is perfectly aligned with a 125 MHz clock edge, then there should be no problem. If you are transferring data from the 12.5 MHz domain to the 125 MHz domain (for example), and the 125 MHz clock lags the 12.5 MHz clock by just the right amount (roughly the propagation delay of the internal FFs), you could indeed have metastability problems. Furthermore, if the relative delay of the two clocks is fixed, and you're in a problem zone, synchronization FFs may not work well, since every transfer will be problematic.

In this case, you could work around it by synchronizing with a FF driven by the opposite clock polarity, since if the rising edge is guaranteed a problem then the falling edge is guaranteed good - as long as the metastability region is less than 1/2 clock period wide, 4 nsec in this case.

At any rate, you need to do a careful analysis of your clock generator.