Since you use a PLL to generate your 12.5MHz clock, the phase relationship will be kept by the synthesis tool, whatever it is. This means the timing analysis will properly report any path between the two clocks and will tell you if it can't satisfy the setup/hold relationship. The clocks will also likely be edge-aligned, but this depends on the PLL's configuration.
It is easy to perform a clock-domain transfer between an edge-aligned 12.5MHz to 125MHz. If the source setup within 8ns, the 125MHz will latch the value without problem. The other direction is also easy, except you must keep any value for 10 125MHz clock-cycles to make sure the slower clock latch the new value (the tool won't verify this).
It is sometimes preferable to consider the two clocks asynchronous. An example case would be if the clock ratio is 11/13, it may be impossible to satisfy timings between the clocks. In that case, just consider them asynchronous, put false path constraints and use FIFOs, synchronization registers or any other technique to transfer data.
In your case, consider them synchronous, it shouldn't be difficult to meet timings if they are edge-aligned or if their phase relationship isn't utterly bad. Also be sure to verify the timings report, if the cross-domain paths aren't there, then you know there is something wrong.