# Significance of -1 slope in CMOS inverter transfer characteristics

In the CMOS inverter transfer characteristics what is the significance of slope of $-1$ at the points where $V_{IH}$ and $V_{IL}$ have been shown? And how is this the occurrence of the values, $V_{IL}$ and $V_{IH}$ related to the point where the slope is $-1$?

This seems to be the standard textbook definition of VIH and VIL. Using a slope of -1 as the limit makes more sense if you think of inverters as amplifiers and remember that the input will have some noise:

simulate this circuit – Schematic created using CircuitLab

Going back to your graph, if the input voltage is between VIH and VIL, any noise will be amplified. If the signal passes through many gates (which it probably will), the noise could be amplified enough to flip a bit. This leads to the definition of the noise margins for the inverter:

$$NM_H = V_{OH} - V_{IH}$$ $$NM_L = V_{IL} - V_{OL}$$

Or at least, that's my understanding. I found some sources that said choosing a -1 slope as the threshold maximizes the sum of the noise margins $(NM_H + NM_L)$, but I'm not sure how that works.

There seems to be a lot of debate among textbooks and academics about how best to define $V_{OH}$ and $V_{OL}$. Some sources define them as the extreme limits of the output voltages, while some use the same -1 slope definition as the input thresholds. (The latter seems to be more formally correct.) I even found an IEEE paper which claims that all of the definitions are wrong, including the input thresholds!

I don't have a resolution to all this except to say that the significance of the -1 slope definitely has to do with noise margins. I believe that answers the original question.

While I can't be sure, since you have provided no context or links to the original source, I would guess that this is part of a discussion on how to quantify 3 terms: input high, input low, and mid-voltage.

What the author seems to have done is to take the position that, for a logic circuit, there will be input/output high and low regimes, where changing the input has little or no effect on the output, and a middle area where the output is sensitive to changes in input. Apparently the author has chosen to define the input high and low thresholds as those at which the change in input is equal to change in output - where the slope of input vs output is -1. The mid-point, where the input equals the output, is obviously where the curve intersects the line Vin = Vout; in otherwords where it intersects a line with slope = 1 and which intersects the origin.

This is a generalized approach to analyzing response curves, and has the advantage of dealing in a consistent way with curves which are not ideal. An ideal inverter, for instance, has an input/output curve with flat in the high and low regions and a vertical transition region. For such a devices, Vil, Vm, and Vih are the same. But real devices don't have infinite gain, and your figure seems to be one way to deal with this.

Note that this is not the only way to deal with the problem. You might, for instance, define the transition points as those which produce outputs of 10% and 90% of the output range, and Vm as the 50% point. Or any other set of values you like.

• what kind of source are you to here,of which i have not provided the link. I would like to make it as descriptive as possible – Abhishek Tyagi Jun 10 '15 at 16:02
• I'm sorry, I don't understand the question. You provided no source for the diagram, and I certainly don't know where to find it. – WhatRoughBeast Jun 10 '15 at 16:13
• ok....actually it is a book named "Microelectronics circuits" by Sedra Smith – Abhishek Tyagi Jun 10 '15 at 16:35
• I still don't understand the question. – WhatRoughBeast Jun 10 '15 at 17:44

The "slope=1" comment indicates that the diagonal line shows the point where Vin=Vout. If one has two inverters in a back-to-back configuration to form a latching circuit (to change the latched state, use stronger transistors to overpower the latching transistors), both inverters could sit at that precise voltage indefinitely. If one inverter's input was a little higher, that would cause its output (the other inverter's input) to go a little lower, which would in turn cause the that inverter's output (the first inverter's input) to go higher, etc. eventually causing the latch to fully switch, but if the voltages are both infinitesimally close to the Vin=Vout voltage, switching could take an arbitrarily long time.

The places where the slope of the transfer function is -1 define Vil, Voh, and Vih, though it's not quite clear whether there's any special significance to the spot where the slop passes negative unity beyond the fact that on every gate with whose transfer function's second derivative is monotonic, and whose output voltage range is as large as its input voltage range, will have such points.

I also see no specific significance in the points having a slope of -1, The most important point of this transfer curve is the point "VM" where input voltage=output voltage. This property of the CMOS transfer curve is used to bias the CMOS unit and to use it as a "linear" amplifier because this point - more or less - is in the middle of the Quasi-linear part of the transfer curve. Simple biasing is possible using a large resistor between input and output of the CMOS device. This gives a stable bias point for amplification of an input signal - either connected via a coupling capacitor or via an additional resistor. In the latter case, due to negative feedback the gain is smaller but has a value that can be selected (and fixed) by the resistor values (opamp principle).

The output remains relatively unaffected with noise if the small signal model gain (dVout/dvin) of the circuit remains below unity. In the figure, the slope of the VTC begins from zero, becomes more negative above VIL, and it approaches zero again when Vin>VIH. That is why some designers consider the limits of margin noise at slope=-1.

• Welcome to EESE. However, I hope you realize that you are answering a >3yr old question that already had a detailed accepted answer. – Edgar Brown Feb 1 '19 at 20:58