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In vhdl code for synchronous counter, I replaced following part

process(clock)
begin
    if(clock'event and clock='1')then
        count <= count + 1;
    end if;
end process

with

process(clock)
begin
    if(clock='1')then
        count <= count + 1;
    end if;
end process

result remains same. Then why 1st way of coding using clock'event is always recommended. ?

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  • \$\begingroup\$ Are you sure the result is the same? Are we speaking of simulated result or some logic gates implementation of that code? \$\endgroup\$ – Vladimir Cravero Jun 10 '15 at 9:10
  • \$\begingroup\$ The combination of both is to specify rising edge. clock'event is any change on clock, and clock='1' is logic level. So any change that results in logic high = rising edge. \$\endgroup\$ – efox29 Jun 10 '15 at 9:13
  • \$\begingroup\$ simulated result @VladimirCravero \$\endgroup\$ – tollin jose Jun 10 '15 at 9:14
  • \$\begingroup\$ "clock'event is any change on clock" but same thing is taken care if we include clock variable in sensitivity list of process. Am I wrong? @efox29 \$\endgroup\$ – tollin jose Jun 10 '15 at 9:16
  • \$\begingroup\$ I thought that you needed at least one 'event for any of the signals in the sensitivity list, either I am wrong or you are using a strange simulator... I'd say my memory is failing here. \$\endgroup\$ – Vladimir Cravero Jun 10 '15 at 9:24
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The sensitivity list is mainly a concept used by simulator to schedule the execution of processes. A synthesis tool will usually discard the sensitivity list.
What are the results when running the above code snippets through a synthesis tool? The implementation without 'event will infer a latch, because that's what a synthesis tool "sees" when looking at the code.

Results of Xilinx XST for if clk'event and clk = '1' then:

Adders/Subtractors : 1  
8-bit adder        : 1  
Registers          : 1  
8-bit register     : 1 

Results of Xilinx XST for if clk = '1' then:

Adders/Subtractors : 1  
8-bit adder        : 1  
Latches            : 8  
1-bit latch        : 8

The results above where obtained by synthesizing an 8 bit up counter.

EDIT (2015-06-11): In IEEE-1076.6-1999 "IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis" the expressions which "shall represent a positive clock edge when used as a condition in an if statement" are explicitly defined as:

  • RISING_EDGE( clk_signal_name )
  • clk_signal_name'EVENT and clk_signal_name = '1'
  • clk_signal_name = '1' and clk_signal_name'EVENT
  • not clk_signal_name'STABLE and clk_signal_name = '1'
  • clk_signal_name = '1' and not clk_signal_name'STABLE
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  • \$\begingroup\$ What do you mean that it infers a latch? I don't understand \$\endgroup\$ – JobHunter69 Nov 27 '17 at 0:08
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Starting with the definition of VHDL from wikipedia

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

VHDL is used mainly to describe digital circuits for ASIC or FPGAs but it can be used for digital-analogic systems (mixed-signal) or even be used to describe parallel processes.

'event means a change in a digital signal, that is an edge. Combined with '1' you define a rising edge. This is almost the same as the rising_edge(clk) function. Here the slight difference between them (for advanced user).

So, if you don't use 'event, you are describing a process activated during the high level of clk. For example, for a 40MHz clock 50% duty cycle, the clock is in '1' state during 12.5ns. What happen to the counter during these 12.5ns? How many times will count during these 12.5ns? And the most important, the system to which these code have been wrote is capable to increment a counter using a clock level? Probably not, although your simulator gives you the same results. Be careful with simulator results, because simulators are different to synthesizers and can provide very different results.

VHDL is a generalist language that is used widely to describe digital circuits. So, each manufacturer have their optimal templates to describe counters, registers, memories... And clock'event and clock='1' or rising_edge(clk) are de-facto standard to describe a rising edge of a signal listed in the sensitivity list. In the same way, if you describe an asynchronous reset, you put reset signal in the sensitivity list and a high or low level that initialize the register all the time the signal is asserted, not in a instant defined with an edge.

process (clock, reset) 
begin
   if reset='1' then 
      count <= (others => '0');
   elsif clock='1' and clock'event then
      <count> <= <count> + 1;
   end if;
end process;

To summarize, each programmable logic manufacturer use a limited and defined set of VHDL definitions to describe their systems. I recommend you to search for the VHDL or Verilog templates for Xilinx or Altera. These templates are correctly understood by synthesizer to be translated to elements of a particular programmable logic chip, or ASIC or other systems.

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  • \$\begingroup\$ There are inconsistencies in that quoted 'authority' looking up it's terms in Wikipedia itself. What is a general purpose programming language can overlap with a domain specific language, the only domain that occurs for in VHDL is in describing hardware. 'Can you implement a VHDL analyzer, elaboration and simulater in VHDL?' And no you can't, though you can describe hardware to do these things, the hardware would be huge - too big and slow simulating instead of executing as in a C implementation, not a domain specific language. Delta cycles emulate parallelism, that requires signal events. \$\endgroup\$ – user8352 Jun 10 '15 at 18:39
  • \$\begingroup\$ What do you mean? Are you saying is better describe a parallel system in C instead than VHDL? I will wonder if could be created a more agile workflow or language to describe hardware or parallel processing circuits. I fact I'm expecting that. HLS software aren't mature enough to provide optimal results. \$\endgroup\$ – David Quiñones Jun 11 '15 at 14:38
  • \$\begingroup\$ I'm saying the supporting quotation for your answer isn't applicable. \$\endgroup\$ – user8352 Jun 11 '15 at 14:54
  • \$\begingroup\$ You are referring about the quote "general purpose parallel" quote? I'm not expert about these aspect of VHDL. Maybe in her origins was thought in that way. \$\endgroup\$ – David Quiñones Jun 12 '15 at 12:47
  • \$\begingroup\$ To be strict we must refer to the VHDL standard. All the same, the aim is clarify that each simulator and each synthesizer interpret on their way, and sometimes with very different results, because the standard is generalist and don't cover what to do in all cases. \$\endgroup\$ – David Quiñones Jun 12 '15 at 13:18

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