In vhdl code for synchronous counter, I replaced following part
process(clock)
begin
if(clock'event and clock='1')then
count <= count + 1;
end if;
end process
with
process(clock)
begin
if(clock='1')then
count <= count + 1;
end if;
end process
result remains same. Then why 1st way of coding using clock'event is always recommended. ?
The sensitivity list is mainly a concept used by simulator to schedule the execution of processes. A synthesis tool will usually discard the sensitivity list.
What are the results when running the above code snippets through a synthesis tool? The implementation without 'event will infer a latch, because that's what a synthesis tool "sees" when looking at the code.
Results of Xilinx XST for if clk'event and clk = '1' then:
Adders/Subtractors : 1
8-bit adder : 1
Registers : 1
8-bit register : 1
Results of Xilinx XST for if clk = '1' then:
Adders/Subtractors : 1
8-bit adder : 1
Latches : 8
1-bit latch : 8
The results above where obtained by synthesizing an 8 bit up counter.
EDIT (2015-06-11): In IEEE-1076.6-1999 "IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis" the expressions which "shall represent a positive clock edge when used as a condition in an if statement" are explicitly defined as:
Starting with the definition of VHDL from wikipedia
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
VHDL is used mainly to describe digital circuits for ASIC or FPGAs but it can be used for digital-analogic systems (mixed-signal) or even be used to describe parallel processes.
'event means a change in a digital signal, that is an edge. Combined with '1' you define a rising edge. This is almost the same as the rising_edge(clk) function. Here the slight difference between them (for advanced user).
So, if you don't use 'event, you are describing a process activated during the high level of clk. For example, for a 40MHz clock 50% duty cycle, the clock is in '1' state during 12.5ns. What happen to the counter during these 12.5ns? How many times will count during these 12.5ns? And the most important, the system to which these code have been wrote is capable to increment a counter using a clock level? Probably not, although your simulator gives you the same results. Be careful with simulator results, because simulators are different to synthesizers and can provide very different results.
VHDL is a generalist language that is used widely to describe digital circuits. So, each manufacturer have their optimal templates to describe counters, registers, memories... And clock'event and clock='1' or rising_edge(clk) are de-facto standard to describe a rising edge of a signal listed in the sensitivity list. In the same way, if you describe an asynchronous reset, you put reset signal in the sensitivity list and a high or low level that initialize the register all the time the signal is asserted, not in a instant defined with an edge.
process (clock, reset)
begin
if reset='1' then
count <= (others => '0');
elsif clock='1' and clock'event then
<count> <= <count> + 1;
end if;
end process;
To summarize, each programmable logic manufacturer use a limited and defined set of VHDL definitions to describe their systems. I recommend you to search for the VHDL or Verilog templates for Xilinx or Altera. These templates are correctly understood by synthesizer to be translated to elements of a particular programmable logic chip, or ASIC or other systems.
