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I have a couple of memory IC's lying around (16 of them) which I would like to use in my homebrew Z80 project. These IC's were produced by Samsung in 1988, the KM41256A 256K x 1 bit. I realise I can't hook them all up as the Z80 can't address more then 64K and I'd still like a rom and some IO.

However, I thought I'd use 4 of them to create 16K which seems enough for a test setup. I know I'd need a line decoder for the chip select pins but I'm a bit at a loss how to approach this.

My questions:

  1. First and for most would it even be possible to use these chips? Or do I need chips with a word equal to the data width of my Z80 (surely this can't be true?).
  2. How much address lines would I need to address 16K of memory?
  3. Which line decoder would I need 2-to-.... ?

I hope I phrased the questions in such a way that they're understandable. I'm completely new to this type of design. I've tried to read up online as much as I could but these matters left me confused.

Thanks.

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    \$\begingroup\$ You'll have a much simpler task if you use 8 of them. \$\endgroup\$ – Brian Drummond Jun 10 '15 at 20:26
  • \$\begingroup\$ Thanks @BrianDrummond for the reply, I do have 8 of them :-) I thought I'd limit to 4 to save space on the PCB. But any answer is welcome, also using 8 chips \$\endgroup\$ – Thomas Cremers Jun 10 '15 at 20:29
  • \$\begingroup\$ The extra logic you'll need to use 4 (unless you hide it in an FPGA) will easily wipe out that space saving! \$\endgroup\$ – Brian Drummond Jun 10 '15 at 23:51
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These 256K x 1 chips are only 1 bit wide. With four of them you would only get 1 nibble at a time, and the Z80 doesn't do 4-bit data.

It is possible to use them, but not what I'd call practical, and would take far more than 8 chips, unless you want to use an FPGA to make a RAM controller. You need a controller anyways, in order to generate your dynamic RAM timing. But let's concentrate on simple read/write operations.

You need, at a minimum, a 9-channel 2x1 multiplexer for the addresses. You also need some time delays to generate RAS and CAS strobes. With a single 41256 you could produce a 32K x 8 RAM, by using page mode. Using the upper 15 address bits as the 32K address and the 3 lsbs of address to provide the 8 bits of data, you would perform a page mode read or write , then step through the 3 data addresses to sequentially read or write the 8 data bits into or from the RAM. Page mode cycle time takes 100 to 150 nsec/cycle, depending on your chip speed, so a single read or write cycle would take on the order of 1 to 1.5 usec.

Chip count would be something like: 2 ea. 74HC157 2-1 mpx (although this would restrict you to a 16k equivalent), 1 ea 74HC374 for the RAS addresses, 2 ea 74HC161 for the CAS addresses, 1 ea. 74HC161 for the data bit counter, 1 ea 74HC151 8-1 mpx for writing data, 1 ea 74HC374 as a read shift register to store the output data before sending it to the Z80, and a 74HC244/245 to drive the data onto the Z80 data bus. Plus a few more for glue logic, at a guess. That's a minimum of about 11 chips. Plus, assuming you're using an 8-MHz Z80, it will run at an equivalent of about a 2-MHz chip. All your memory reads and writes will take a loooong time.

You can, of course, speed things up by using 4 of them with a two-stage read or write cycle with almost no loss in speed.

What you really need to do is use 8. Then you have a good match between your CPU and your memory, and you should be able to get decent speed and minimal chip count.

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  • \$\begingroup\$ thanks for the elaborate answer. My motivation for using 4 chips was to keep it simpel and safe board space, this seems to be a case where less isn't more :-) From both answers it's clear that if I want to use these chips I should really go for the 8 chip option. Or even better just order a 64x8 parallel ram chip (I was surprised what those cost). In any case, thanks again for the explanation \$\endgroup\$ – Thomas Cremers Jun 11 '15 at 12:41
  • \$\begingroup\$ A 64 x 8 will indeed cost you, since those are very old and not much produced. A 32k x 8, on the other hand, such as the Toshiba TC5525 can be found cheap on eBay. And since it's static, you don't need any logic for RAS/CAS generation or address multiplexing. \$\endgroup\$ – WhatRoughBeast Jun 11 '15 at 12:49
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As a MOS Tech 6502 adept you would have been the enemy in the early 80's! ;-) If I remember well, the Z80 memory were dynamic RAM chips. So you need to update the rows every so many milliseconds and need a special chip to do that. Not sure if you need an even number of address lines (row+column) per se to do that. 16k (note the lower case k for kilo, K is for Kelvin) is 2^14, so 7 rows and 7 columns to scan and you have your Nibbles (half byte). You need to go to 8+8=16 and 2^16=64k Nibbles to cover for 16k Bytes. Or 7+8 and 2^15= 32k Nibbles if unequal row/column are allowed. Given the speed of modern chips you can multiplex two Nibbles into a byte, but you need to do that bi-directional (R/W). This may become complex and not realy a space saver. So I would go for the 8-chip approach as suggested by Brian.

PS. For the 6502 we used static memory. Easier to use but more expensive :-)

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  • \$\begingroup\$ thanks for the detailed answer! It seems that my own nostalgia made it all a bit more complicated. The memory chips are from my old Amiga 500 memory expansion ;-) Love the enemy of the 80s comment though ;) \$\endgroup\$ – Thomas Cremers Jun 10 '15 at 21:55
  • \$\begingroup\$ The Z80 does not require DRAM, but it does have the advantage (over the 6502) of having a refresh counter built in, which greatly reduces the complexity of the external hardware required to support DRAM. There are many examples on the web; for example, I have the schematics for the Ferguson BigBoard on my website. \$\endgroup\$ – Dave Tweed Jun 10 '15 at 22:36
  • \$\begingroup\$ @DaveTweed, thanks for the resource! I'm looking into it and it seems to have the detail level I was looking for :-) z80.info also has a lot but it's a bit like a needle in a haystack ;-) \$\endgroup\$ – Thomas Cremers Jun 11 '15 at 12:45

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