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In the wikipedia page for EEPROM: http://en.wikipedia.org/wiki/EEPROM it is given that "Parallel EEPROM devices typically have an 8-bit data bus and an address bus wide enough to cover the complete memory" and also "Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM". In that case why are serial EEPROMs becoming more popular than the parallel EEPROM?

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    \$\begingroup\$ They require less pins and various serial busses are very common in designs. With modern speeds the speed of serial is absolutely fine for what EEPROM devices are used for. \$\endgroup\$ – David Jun 11 '15 at 10:58
  • \$\begingroup\$ Surely with the same modern speeds a parallel interface would give a much better throughput, compared to a serial interface? \$\endgroup\$ – Arpith Jun 11 '15 at 11:02
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    \$\begingroup\$ Sure, but if you don't need speeds faster than serial gives then why waste pins? \$\endgroup\$ – David Jun 11 '15 at 11:09
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    \$\begingroup\$ ... that's why we've got USB, not UPB \$\endgroup\$ – Chu Jun 11 '15 at 11:31
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    \$\begingroup\$ And serial ATA, PCI express etc. \$\endgroup\$ – David Jun 11 '15 at 11:51
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It is very simple. Number of pins and cost of packaging.

EEPROM devices are primarily used to store parametric data or characterization constants for a device. The typical scenario is to write very seldom and read typically once each time the host device boots up. For this type of application the relatively slow writing times of EEPROM are of little concern. And the reading time to load at most a few K-bytes of data from a serial device (SPI or I2C) is not normally an excessive time impact.

There is another factor that has played into the popularity of serial devices over parallel devices. That has been the migration of MCU devices from older microprocessor units with parallel busses to the much more prevalent modern types that have all their program storage memory and data memory built right on the chip. Often there is no longer a parallel bus option directly available. And in most applications there is very little interest in using up scads of pins to bit bang to a parallel peripheral.

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  • \$\begingroup\$ You mean the only deciding factor here is the real estate the pins occupy? \$\endgroup\$ – Arpith Jun 11 '15 at 11:00
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    \$\begingroup\$ @Arpith That's not an insignificant consideration. A parallel 32 kilobit EEPROM would require 20+ pins and a correspondingly large package; a serial one requires two. \$\endgroup\$ – Nick Johnson Jun 11 '15 at 11:14
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    \$\begingroup\$ @MichaelKaras: +1 for the last para for your answer (didnt find this information anywhere). Any sources/ references to help me learn more about EEPROM types? \$\endgroup\$ – Arpith Jun 11 '15 at 11:23
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    \$\begingroup\$ Also, you can daisy-chain SPI devices and have multiple I2C devices on a bus, further saving pins. \$\endgroup\$ – pjc50 Jun 11 '15 at 11:52
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    \$\begingroup\$ The real estate required to route the extra traces for a parallel package can be significant is some applications as well. \$\endgroup\$ – semaj Jun 11 '15 at 15:54
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In the early days, wires were cheap and transistors were expensive. These days it's the reverse. Hence why almost everything is done serially.

In the early days, chips weren't very sophisticated, and a CPU would power up and read the first thing it found on its memory bus at the starting address, so parallel EEPROMs effectively mimicked the DRAM that was hanging on the bus.

These days, DDR RAM is screaming away at gigahertz on huge wide buses, making a flash chip that could hang on the same bus would be prohibitively expensive and fairly pointless when modern CPUs have enough built-in intelligence (thanks to cheap small transistors) to boot from I²C/SPI flash.

With micros, these days the program flash and RAM is usually internal to the device. External storage like EEPROM can hang on an I²C bus, saving I/O pins for other functions whilst maintaining acceptable throughput. The fewer I/O pins you use, the smaller, cheaper and more energy efficient you get. Plus it's far easier to track two wires around a board than two 8/16/32-bit wide buses, with the associated EMC issues, etc., etc.

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  • \$\begingroup\$ If a processor needs to use a memory bus to access its main memory, and if that memory bus is slow enough that capacitive loading isn't a particular issue, interfacing a parallel EEPROM that is designed to be written "in-system" will in many cases be easier and cheaper than interfacing a serial one. Address-decode signals are often generated in groups of eight, and if one has a spare address-decode signal available, adding a parallel EEPROM may require zero extra circuitry. \$\endgroup\$ – supercat Jun 11 '15 at 18:35
  • \$\begingroup\$ The PC boot memory is a somewhat unusual application, though an interesting aspect of it is that some processors have highly-configurable buses and have enough cache RAM to hold a significant amount of code without using the main external bus at all. If the processor can get some initial code loaded before it has to use the external bus, that code can then configure the bus characteristics to match the physical hardware configuration. \$\endgroup\$ – supercat Jun 11 '15 at 18:38
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Don't forget there is a "half-way house" called SQI. That is a multiple parallel bit serial interface (it stands for Serial Quad Interface).

From a protocol point of view it is just the same as working with a normal serial interface, but instead of just one bit being transferred every clock, 4 bits can be transferred at once. Instead of a single data/clock, or din/dout/clock arrangement it has 4 data pins and one clock. This gives 4x the through put of a normal serial interface and doesn't require many more pins. In fact many SPI flash chips can also run in SQI mode without requiring any more than the existing 8 pins they already have. A significant increase in speed without any increase in real estate.

SQI is becoming a popular interface for faster loading of programs from external flash chips - not only used for simple microcontrollers, but also now often used for booting the BIOS of PCs, especially laptops, where space is a real concern.

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  • \$\begingroup\$ Wow. This I hadnt heard of. \$\endgroup\$ – Arpith Jun 12 '15 at 6:00
  • \$\begingroup\$ SQI will offer 4x the throughput of serial flash when fetching data sequentially, but an 8-bit-wide parallel flash may still be an order of magnitude faster when one byte each from many "random" locations. \$\endgroup\$ – supercat Jun 21 '15 at 21:06
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The low pin count on the device itself is probably less important than the saving on the MCU or FPGA you connect it up to.

Finding 8 data pins, plus many more address, select and enable pins means a much bigger package and probably more expense for the MCU too.

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While parallel EEPROM chips are faster and less complicated to communicate with, serial ones are less expensive hardware-wise, as they require less pins, energy, and wires/circuits.

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Just for grins, let's say I have an old-timey 2-way radio in my airplane, with 16 frequencies available and selectable from the cockpit, where the control unit resides.

Aft, somewhere, is the transmitter-receiver unit with a cable running to the control unit containing, among other things, the 16 wires running to the cockpit selector switch required to do the frequency selection.

One day, when talking to a friend, I bring up the subject of the radio and ask him if it wouldn't be possible to encode the cockpit frequency settings into a four bit binary number and send that number over four wires (saving 12 wires) to the T/R unit where it would be decoded into the sixteen signals needed to do the frequency selection.

"Sure", he says, "but why stop there? instead of sending the [four bit] number all at once, why not send it a bit at a time over a single wire and have the decoder in the T/R unit figure out the frequency to select, saving 15 wires in the cable and 15 pins each in the connectors connecting the units?"

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Below are some reasons why serial EEPROM is preferred over parallel EEPROM.

  1. Lower Current Consumption. For example, operating currents for 16K serials are around 3 mA; the same for 16K parallel devices is approximately 30 mA and above. So the lower the current, the lower the power consumption.

  2. Lower Voltage - serial EEPROMs are available in the markets which operates on low voltages (1.8-2.5 V). Low voltage operation also has a positive effect on power consumption.

  3. Programmability - serial EEPROMs are easier to program compared to parallel. Serial EEPROMs have the ability and ease of programming one byte at a time;

  4. Serial EEPROMs are available in smaller footprint

  5. Lower pin count

  6. Available at a lower price compared to parallel ones

  7. Low microcontroller overhead and support

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  • \$\begingroup\$ Point 2 is probably incidental. There's no technical reason why parallel EEPROMs would need a high voltage. But low-voltage EEPROMs target the low-power market, and by reason 1 those low-power EEPROMs happen to be serial. \$\endgroup\$ – MSalters Jun 11 '15 at 14:41
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    \$\begingroup\$ I'm not sure Sanjeev is comparing like-for-like devices here, if they're even available. Parallel eeproms are quite old-hat whereas serial ones are a more modern phenomena generally, so saying a 1980's 16k device is less efficient than a 2015 16k device is a bit of a false comparison, they're likely to be using completely different technologies.... \$\endgroup\$ – John U Jun 11 '15 at 15:15
  • \$\begingroup\$ What is the unit for "16K"? Is it 16 kilobits? 16 kilobytes? \$\endgroup\$ – Peter Mortensen Jun 11 '15 at 20:38
  • \$\begingroup\$ It is 16 kilobytes. \$\endgroup\$ – Sanjeev Kumar Jun 12 '15 at 3:51
  • \$\begingroup\$ @ John This comparison was not based on time. Even if you look in to the older serial EEPROMs, they do not work at lower voltages. This comparison is only based on technology what is available today. \$\endgroup\$ – Sanjeev Kumar Jun 12 '15 at 3:56

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