It seems that the world has decided that
std_logic_vector) are the default way of representing bits in VHDL. The alternative would be
std_ulogic, which is not resolved.
This surprises me because usually, you're not describing a bus, so you do you don't want multiple drivers and you don't need to resolve a signal. The advantage of
std_ulogic would be that the compiler warns you early on if you have multiple drivers.
Question: is this just a cultural / historical thing, or are there still technical reasons to use std_logic?