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I'm a student trying to learn Verilog on my own with a dev board. This is just a simple and short module. I just need some clarifications.

module BASIC (CLOCK_50, KEY, LEDG);

input CLOCK_50;
input [3:0] KEY;
output reg [8:0] LEDG;

reg [2:0] key0_dly;

always @(posedge CLOCK_50)
begin
  if (!key0_dly[2] && key0_dly[1])
    LEDG[0] <= ~LEDG[0];
    key0_dly <= {key0_dly[1:0], KEY[0]};
end
endmodule

now I know the basic syntax of Verilog. My questions would be:

  1. What is the purpose of key0_dly? Why does the if statement check the 2 bits of it?

  2. Why is key0_dly assigned the values {key0_dly[1:0], KEY[0]}? What does that line do?

  3. Is this line key0_dly <= {key0_dly[1:0], KEY[0]}; in the if statement? Am I correct in saying that if there is no begin and end then like in C only the one line of code that follows in the if block?

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    \$\begingroup\$ Your indentation is a bit misleading. \$\endgroup\$ – copper.hat Jun 15 '15 at 6:40
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  1. What is the purpose of key0_dly? Why does the if statement check the 2 bits of it?

It wants to complement LEDG[0] only if the trigger has occurred during the previous loop but not 2 loops ago. Looks like simple debouncing/edge detection to me.

  1. Why is key0_dly assigned the values {key0_dly[1:0], KEY[0]}? What does that line do?

It left-shifts key0_dly one bit, shifting the value of KEY[0] in.

  1. Is this line key0_dly <= {key0_dly[1:0], KEY[0]}; in the if statement? Am I correct in saying that if there is no begin and end then like in C only the one line of code that follows in the if block?

Sounds right. But you need the shift to happen each loop otherwise there will be no way to trigger the condition.

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  • \$\begingroup\$ Minor point: I think it detects if the trigger (a rising edge) occurred two cycles ago, not in the previous. \$\endgroup\$ – copper.hat Jun 15 '15 at 7:38

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