# How do I determine if the clock signal suffers from high speed effects

I need to determine if the clock signal inside a multichip module shall suffer from high speed effects i.e reflection and ringing. I have:

(1) IBIS models of the components inside the multi-chip module

(2) The IBIS models in (1) converted to PSpice Models

(3) length of PCB tracks of the clock signals and the propagation delay on them and their characteristic impedance

(4) Cadence Design suite with the following software:

Allegro PCB Planner
Design Entry CIS
Design Entry HDL Rules Checker
Design Entry HDL
FPGA System Planner
Library Explorer
Package Designer
PCB Editor
PCB Route
PCB SI
Physical Viewer
Project Manager
SiP Digital Architect
SiP
System Architect


There are also some more directories

AMS Simulator
PCB Editor Utilities
PCB SI Utilities
PSpice Accessories


What do I do next to carry out this signal integrity simulation? If the clock signal starts from the oscillator and then after a few milimeters, splits into multiple tracks which connect to different components, does that cause impedance discontinuity and thus high speed effects?

• Branching off is an immediate discontinuity and so you will get reflections. How long the branches + edge time will determine if its an issue or not. If the clocks are critical, consider a clock buffer and do point to point connections. Jun 15 '15 at 21:56
• The design is done and it works, I just need to do a simulation to show some external people that well, it will not suffer from high speed effects. How do I model the transmission line I mean the PCB track? How do I model a PCB track that splits? I really don't know how to do this in SPICE. Or perhaps the Cadence Design Suite has some special software to do this??? Jun 15 '15 at 22:03
• If the board is already done, then you can show them its performance or take scope measurements. And I would suspect if you aren't already familiar with this sort of thing, the simulation might give you false simulation readings due to incorrect modelling. How would you then know it was modeled correctly ? Can you not show them physical performance ? Jun 15 '15 at 22:07
• Physical measurements are difficult. it is a multi-chip hybrid i.e a package with multiple dies inside on a single substrate. You said "How would you then know it was modeled correctly?", that is why I have posted this question here. Jun 15 '15 at 23:51