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I've read before that "every IC" should be decoupled. I've never before bothered on gates, buffers, etc. No datasheet that I've read for those chips has ever suggested to do so, until I came across a TI buffer chip that suggested putting a cap across power and ground. That got me wondering if that's just common best practice anyway?

Should I be putting a cap between every VCC/GND I come across, no matter what? Or it just isn't that important?

Specifically I wonder then why, for example, a buffer 14-pin almost always has the VCC and GND chips on completely opposite corners. If it was the design intent to decouple it, shouldn't they be adjacent?

My experience tells me it can't possibly be that important, since I've never done it and I have devices operating reliably for years in the field... but always looking to improve.

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    \$\begingroup\$ sorry buddy, but you're experience is misleading you. I'll try and post an answer later. But decoupling caps should always be used. \$\endgroup\$ – efox29 Jun 15 '15 at 22:18
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    \$\begingroup\$ My experience is just the opposite: without bypass caps, ICs don't work reliably. Must be close to the IC too, like within 20mm or an inch, otherwise they don't decouple the parasitic inductance well enough. \$\endgroup\$ – MarkU Jun 15 '15 at 22:28
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    \$\begingroup\$ pCB layout using DIP packaged parts used to be placed in a column, with the Vcc and Gnd route along the length of the package, underneath the die. Then radial-leaded cap across those routes, between each IC. That's why pins 7 and 14 were used for Gnd and Vcc. \$\endgroup\$ – MarkU Jun 15 '15 at 22:32
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    \$\begingroup\$ Solderless breadboard uses slightly different technique, radial-leaded capacitor with longer leads, installed directly over the IC from 14 to 7. \$\endgroup\$ – MarkU Jun 15 '15 at 22:34
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    \$\begingroup\$ Yes. Simple rule to live by :) \$\endgroup\$ – KyranF Jun 15 '15 at 23:26
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I always put decoupling caps (usually 100 nF) on every power pin, not just logic IC's but also analog ones like op-amps.

The only exception is when you have two IC's adjacent to each other, and the power pins end up so close together that you would be placing two decoupling caps almost on top of each other, you can get by with just one.

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Explicit power supply decoupling is less important at lower operating frequencies, but as the speed of transitions in your circuit rises the effect of high-frequency components of the resultant spikes on your power rails increases and can cause glitches. An appropriately-sized decoupling cap close to each chip's power supply pin(s) will eliminate any problems - so far, "appropriately-sized" for you has meant "negligible", but you've been (some would say un)lucky.

The sub-question about traditional power pin layout on DIP logic I'll leave for somebody else.

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    \$\begingroup\$ Not just the rate of transitions, but even the rise time of a single transition affects the instantaneous current demand. \$\endgroup\$ – MarkU Jun 15 '15 at 22:36
  • \$\begingroup\$ Indeed, +MarkU. I've changed "rate" to "speed" to better reflect this point. \$\endgroup\$ – mlp Jun 15 '15 at 22:53
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    \$\begingroup\$ I'm guessing when you say "some would say un[lucky]" that you're suggesting that the "luck" isn't fortunate because it encourages bad habits. If that's what you meant... solid point. Of course, learning opportunities come in many forms. Where I was truly "lucky" is not that the device worked so much, but that I got to learn this lesson the easy way! \$\endgroup\$ – bcsteeve Jun 16 '15 at 14:18

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