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I've got a circuit I'm developing using an op amp to drive a power MOSFET for an electronic load:

enter image description here

I'd like to test it for stability, but I don't have enough experience to know what perturbations are most likely to show any instabilities.

I have the following ideas:

  • Inject a square wave (offset such that low value is >= 0V) into the non-inverting input while monitoring the voltage on the sense resistor (load current waveform). This would simulate sudden changes in the control voltage (1V/A) likely to be supplied later by a DAC.

  • Apply stepped input voltage to IN+, simulating connection of power supply under test.

Are these sensible ideas that are likely to uncover any op-amp related instabilities?

Also, are there LTSpice simulation exercises that might be worth trying?

UPDATE:

  • I revised the schematic to be more suitable for simulation. I found and used models for the specific parts I'm using and removed all compensation elements for a baseline simulation.

New schematic

  • I ran an analysis feeding a DC-offset square wave into the control pin (non-inverting input in this circuit). The result was dead stable. There's a teeeny-weeeny 1mV overshoot on the rise if you zoom way in, otherwise it absolutely mirrors the input (except it represents current flow of course). I even reduced the rise time to 1ns to see if I could get it to ring, but no luck :)

plot

  • I ran an .AC analysis like @Kevin White suggested, and found a 62 degree phase margin in the open loop gain.

  • I built it up as @mkeith suggested, and unfortunately it oscillates like crazy on the breadboard :) I was able to make some progress stabilizing it a bit until I accidentally blew out my MOSFET. It's down to the store tomorrow to get a new one so I can carry on from there :)

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    \$\begingroup\$ I am kind of an empirical person. I would build the circuit. Step VCC and step IN+. Use a function generator to control a small power mosfet to apply the step. Trigger on the synch output of the function generator. Use averaging to observe the step response. I would also add a "normal" feedback resistor directly from the output to the inverting input. You don't have to populate it. But it could save you if the circuit ends up being unstable or marginal. \$\endgroup\$ – mkeith Jun 16 '15 at 6:24
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    \$\begingroup\$ scanny, regarding correct loop gain simulation read the comments to Kevins answer!. \$\endgroup\$ – LvW Jun 18 '15 at 8:15
  • \$\begingroup\$ scanny, I did some simulation runs of the last circuit. The circuit is stable with a sufficient margin. \$\endgroup\$ – LvW Jun 18 '15 at 9:16
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    \$\begingroup\$ The above comment is the result of a simulation based on a simplified opamp model. Using a REALISTIC model the circuitis, however, unstable! \$\endgroup\$ – LvW Jun 22 '15 at 10:34
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Your methods are fine. What you are looking for in the step response is overshoot or undershoot. What you'd like to see is something approaching critical damping for fast response and good phase margin. Graph borrowed from this SMPS app note.

enter image description here

Your circuit has a strong potential to oscillate- I would definitely add a compensation loop around the amplifier.

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  • \$\begingroup\$ Why do you say the circuit has a strong potential to oscillate? @andy-aka above indicated it looked stable and that's certainly been borne out by the simulations so far. Have we missed something? \$\endgroup\$ – scanny Jun 17 '15 at 16:38
  • \$\begingroup\$ Because of the phase shift caused by the gate resistor. It may be fine, or not, depending on the MOSFET and the resistor value and the op-amp phase margin. \$\endgroup\$ – Spehro Pefhany Jun 17 '15 at 16:41
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    \$\begingroup\$ P.S. it will oscillate as shown with a low load resistance and a MOSFET 5x NXP PSMN063-150D/PLP (typically, in PSPICE simulation). 1x does not. 1K/1n compensation completely cures the instability. Be sure to pay attention to Andy's comments on input and output range of the OP-07 or add a negative supply voltage. \$\endgroup\$ – Spehro Pefhany Jun 17 '15 at 19:34
  • \$\begingroup\$ I couldn't get the PSMD063-150D model to work; it's not built-in on my version of LTSpice and the one I found online just wouldn't work for me. But I did find one for the MOSFET I'm using and got that running. I couldn't get the model to overshoot more than a mV on a 5V/1ns rise, so I'm stumped on that part (although adding a 5uF load capacitor seemed to work :). However on the breadboard it behaves a lot like the picture above! I compensated starting with the values you mentioned (I did need a gate resistor) and it was much better when I blew out my last MOSFET, so need to buy a new one :) \$\endgroup\$ – scanny Jun 18 '15 at 7:43
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    \$\begingroup\$ Turns out you were right @Sphero, the circuit oscillated like a demon when I built it up on the breadboard. I posted another question here electronics.stackexchange.com/questions/176669/… and discovered my LTspice model for the op-amp was an old one without the proper frequency response modeling. I ended up getting it working nicely with a compensation network as you suggested. I think I got it pretty near critical damping. Thanks for your response :) \$\endgroup\$ – scanny Jun 24 '15 at 7:15
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This is normally (all situations that I've witnessed or read about) a stable configuration. The op-amp would be stable with direct feedback so the question is what does the MOSFET add in terms of gain or phase that might make the circuit unstable.

Well, in a source follower configuration the gain of the MOSFET is a little less than 1 so on that score the circuit is still going to be stable. As regards phase shift from gate to source there will be a little but given that the gain has probably reduced about a dB and that the MOSFET is going to be much faster (as a singular device) compared to the op-amp, I really don't think you would have any problems.

It's the sort of circuit that I wouldn't hesitate to build and not expect a decent result. However, in the circuit you have shown I wouldn't use the op-07. It cannot adequately drive its output down to 0V (read the data sheet) and this could mean that the FET is not turned off properly and that control is lost when trying to control small currents.

The same is true (if not more so) when looking at the input voltage range that device is capable of. If you are trying to control 1A thru the 1R sense resistor, the voltage at the OP-07 input is expected to be 1V and this is right on the limit of what the input range can be expected to handle (again read the data sheet).

So my conclusion is don't use an OP-07 or power it with a small negative supply instead of having its neg supply terminal at 0V.

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  • \$\begingroup\$ Thanks Andy; I downloaded and .included an LM358 model to match the component I was planning to use. On simulation it turned out to be dead stable with a step input on the non-inverting input. I'm going to work up a test rig like @mkeith mentioned and see what I get with the real thing :) \$\endgroup\$ – scanny Jun 17 '15 at 16:26
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    \$\begingroup\$ @scanny the LM358 has inputs that work down to the 0V rail and this is a wise selection. The output will also swing down to within 50mV of 0V and this is needed to get full control of the FET. Input offset voltage is a few millivolts and this represents an error in your measurement so be aware of this. The open loop phase response isn't indicated so it usually means at least 45 degrees phase margin and with the MOSFET making possibly another 5 degrees it will still be stable. \$\endgroup\$ – Andy aka Jun 17 '15 at 18:31
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Both of those are good ways to test the stability.

Another thing that can be useful is to measure the open-loop response by breaking the feedback loop by using an extremely large inductor (1Giga Henry for example) then injecting a sine wave at the non-inverting input (with a suitable DC bias) and measuring the voltage across the sense resistor.

You can only break the feedback loop in simulation rather than the real world.

If you put two copies of the schematic in the LTSpice schematic you can do a Bode plot of the closed loop and open loop gains simultaneously.

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  • \$\begingroup\$ "....and measuring the voltage across the sense resistor." What is the next step to evaluate stability properties? Just "measuring" seems to be not sufficient. More than that, this procedure does not realize the classical "loop gain test". \$\endgroup\$ – LvW Jun 16 '15 at 14:47
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    \$\begingroup\$ When I say measuring - I mean both voltage and phase. If you feed in a swept sine wave can get the classical loop gain stability criteria. You can see how close you are to instability just from the transient response with a step input. \$\endgroup\$ – Kevin White Jun 17 '15 at 16:56
  • \$\begingroup\$ Great tip on the .AC analysis Kevin, thanks for that, I'd completely missed that until you mentioned :) Very nice video from Linear Tech on doing that here: linear.com/solutions/4449. Turns out my open loop gain on the circuit with all compensating elements removed is 61 degrees, which explains it's stability in simulation I suppose. Now I can work on why it oscillates so badly on the breadboard :) \$\endgroup\$ – scanny Jun 18 '15 at 7:11
  • \$\begingroup\$ Kevin, you have proposed to open the ac loop (large inductor) and injecting a test signal into the non-inv. input. I like to repeat that this procedure does NOT give the loop gain response. Instead, you must inject the signal (via a large capacitor) into the inverting input and find the ratio between the voltages at both ends of the inductor. Just measuring the output is meaningless! \$\endgroup\$ – LvW Jun 18 '15 at 7:22
  • \$\begingroup\$ The Linear Technologies video linked just above uses a different approach. They break the feedback loop, insert a 0V DC, 1V .AC voltage source and then measure the difference between each end. Might be worth a look, it was simple and quick and I assume the guy knew what he was doing :) \$\endgroup\$ – scanny Jun 18 '15 at 7:46

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