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To be able to connect some peripheral to digital input, I'm designing the circuit protection to avoid any possible failure due to over/under-voltage issue. So, I will add a clamp protection circuit. The requirements I need to accomplish are:

  • Power Source (Vcc): 3V3
  • Max Voltage: 3V9 (3V3 + 0V6)
  • Min Voltage: -0V3 (GND - 0V3)
  • Max Logic input current: +/- 300nA

The circuit is next: Clamp Circuit

R1000 is added to limit the current to 10mA. R1001 is added to limit the input current below 300nA.

My doubts are:

  • Might the circuit be modified in case it need to support up to 30V input?
  • Which would be the best option for both diodes (Forward voltage, breakdown voltage, forward current, etc)?
  • As digital inputs may need to produce a rising interrupt, will be better to add a schottky instead of a zener on D1000?
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  • \$\begingroup\$ Why do you have a maximum logic input current requirement of 300nA? \$\endgroup\$ – Andy aka Jun 16 '15 at 12:07
  • \$\begingroup\$ For Vin = 30 V R1000 will have 30 - 3.9 = 26.1 V across it, 26.1V/330 ohms = ... it will dissipate a lot of power ! You do the calculation :-) R1000 is too low. Indeed the 1 Mohm makes no sense. \$\endgroup\$ – Bimpelrekkie Jun 16 '15 at 12:09
  • \$\begingroup\$ "As digital inputs may need to produce a rising interrupt, will be better to add a schottky instead of a zener on D1000?" You mean: "A rising edge will cause an interrupt". Also, this has nothing to do with using a zener or a shottky diode. \$\endgroup\$ – Bimpelrekkie Jun 16 '15 at 12:23
  • \$\begingroup\$ Rimpelbekkie, you're right. - Power dissipation will be high. - So, in your opinion, I can remove 1Mohm resistor. - And of course, rising edge will cause an interrupt. The doubt here is about the time, Schottky are faster than Zener. \$\endgroup\$ – Yolco Jun 16 '15 at 13:08
  • \$\begingroup\$ Schottky vs Zener: And what do you think, will the interrupt arrive sooner with the zener or the Schottky ? And by how much time ? Does is matter compared to time delay introduced by resistors and GPIO input capacitance ??? \$\endgroup\$ – Bimpelrekkie Jun 16 '15 at 13:32
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This is all you need:

schematic

simulate this circuit – Schematic created using CircuitLab

this also eliminates the problem that a high voltage at the input will lift-up your local VCC.

When input < -0.6 V D1 will conduct and limit GPIO to -0.6 V, R2 limits the current, your GPIO input will be able to handle this (it also has input protection diodes !)

When input > -0.6 V but < 3.9 V D1 does nothing, GPIO also happy

When input > 3.9 V D1 will conduct, R2 will limit any current, GPIO input will be happy.

Someone complained this would not work but was too lazy to explain why but I figured it out myself:

Apparently I overlooked that 3.9 V zenerdiodes leak a lot in reverse so I lowered R1 to 10 kohm. If that still doesn't fix it than you could replace the zenerdiode with 4 to 5 standard diodes in series, see 2nd schematic.

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    \$\begingroup\$ You will not find a Zener that has a hard enough knee for this circuit to be reliable. Have a look at any zener datasheet. \$\endgroup\$ – Spehro Pefhany Jun 16 '15 at 14:07
  • \$\begingroup\$ The zener with minimum forward voltage I have found is 0V9. Although theorically, it should be zener with up to 0V3 Vf. \$\endgroup\$ – Yolco Jun 16 '15 at 14:15
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    \$\begingroup\$ The zener will prevent normal logic levels from getting through. Also it will not be even close to meeting the -300nA requirement with -30V in. These components do not behave in such a simple and ideal manner. \$\endgroup\$ – Spehro Pefhany Jun 16 '15 at 14:18
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    \$\begingroup\$ @SpehroPefhany The zener does not need a "hard knee" voltage. If you disagree, please explain why it will not work. Your statements are nonsense but please, prove me wrong by providing an adequate explanation ! \$\endgroup\$ – Bimpelrekkie Jun 16 '15 at 14:37
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    \$\begingroup\$ I've had some bad experience using zeners of nominal Zv=3.3V or 3.6V because of the "soft knee" they have; they start conducting long before the nominal zener voltage is reached (sometimes as low as 2V) and when the voltage is somewhat higher they cannot keep it low consistently (going as far as 7V when supplied with 16V). When simulated (in LTSpice) they worker perfectly... in the real test circuits they never did. \$\endgroup\$ – MV. Jan 15 '17 at 3:02
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General guidelines being given are generally OK

BUT

You MUST NOT exceed Vdd with any sort of drive capability.
The 3V9 you quote is an ABSOLUTE MAXIMUM value and your controller may well go gaga if you apply that during operation. Look at data sheet in 'typical operating conditions' section and see what limits there are. In a very few datasheets, probably written by marketing men or the office cleaner, they may say 0.2V or 0.3V outside rails is OK BUT more than 0.small is dangerous. Real designers [tm] say 0.0V outside rails in their data sheets.
Experience suggests that the 1M you showed for R1001 is a good idea if you MUST have Vin > Vdd. Still not marvellous but will more often be more liable to be reliable.

Some people argue long and hard that body diode conduction at small currents during operation is OK. Listen to them if you don't care about commercial levels of reliability.

Current in body diodes usually flows into IC substrate and may end up in nodes not usually powered an can trigger spurious FET action where no FET usually exists and can noise up ADCS. These effects are insidious and unpredictable and may be fatal to design reliability. Many "RAD hard" parts (you pay for them in gold) and some others may be designed to specifically target these issues but the large majority are not.

IF your diode clamps allow input voltage to always be
>= Vin_high_min and
<= Vdd_min_actual
(and equivalent for Vin low) for all legal and likely Vin high (and low) during operation then you will be better off than dicing with Murphy.

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  • \$\begingroup\$ @Russel-McMahon, the operating voltage is 3V3, and the logic current for GPIO inputs are +/- 300nA, and the rails are 3V6 & -0V3. 3V9 is the absolute maximum as you said. \$\endgroup\$ – Yolco Jun 17 '15 at 10:56
  • \$\begingroup\$ @Yolco I have not seen a reference to a data sheet or even a part number so I cannot examine your device's specs. You mention operating voltage and rails - I know the words but am not sure how you are applying them here. |Your stated specs SEEM inconsistent -> 3V3 + 0.6, gnd - 0.3- why?. A diagram SHOWING the IC with power connections and labelling ana a part number and link would help zero in on what is really being done. IF you are planning to allow inputs to be 0.65V above the IC Vdd (as seems the case despite apparently conflicting specs) then interesting times may be ahead. \$\endgroup\$ – Russell McMahon Jun 17 '15 at 12:50
  • \$\begingroup\$ @Russel-McMahon, I'm trying to design the best, cost-effective and reduce dimensions, protection circuit for digital inputs IC datasheet. I'm glad with your explanations, but unfortunately this is not a space application (Maybe one day I hope). \$\endgroup\$ – Yolco Jun 18 '15 at 13:25
  • \$\begingroup\$ @Yolco Thanks for the extra input. More anon. Note the Vdd + 0.3 and gnd - 0.3 is on page 9 and nowhere else and is (as I suggested) absolute maximum and may not operate ratings. They do NOT spell out min/max for GPIO but ADC various pins specifically say 0-Vdd (as indeed they should). At Vdd= 3V: Vinhi is 2.5V and Vinlo = 0.5V , so if you can arrange your clamps so Vin hi & lo always meet these you can start clamping them before they reach the rails which allows a somewhat soft clamp knee while still not going beyond rails. This is extreme care and many do not bother but if you want ... \$\endgroup\$ – Russell McMahon Jun 18 '15 at 14:51
  • \$\begingroup\$ ... to be sure that Vin never exceeds spec it can be achieved and the cost is not vast (as long as you do not have tpp many pins involved. | A few weeks ago I lost an ARM with TI WiFi module (started drawing excess current and not processing) (Spark Core, now "Particle") for no obvious reason in a prototype. I have protected most inputs reasonably well and better than many would BUT not perfectly and do not know what caused the death. I have 24V 40 Ah LiFePO4 battery and 250 W solar PV attached so care needed :-). I have seen processors go gaga due to current injected t body diodes. ... \$\endgroup\$ – Russell McMahon Jun 18 '15 at 14:56
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The requirement for maximum +/-300nA input current means that you have to clamp the input voltage to within about +/-100mV of the supply rails (depending on temperature range). If you really need this spec (for example to ensure normal operation during input spikes) then you'll need better clamping than a few resistors and diodes can provide.

I suggest a clamping the inputs with a series resistor and diodes to ground and a shunt regulator such as TL431, then a series resistor to a CMOS buffer. The buffer will not exceed the supply voltages at its output and most can withstand several mA at the input without major malfunctions (they may draw more supply current but they won't latch up).

schematic

simulate this circuit – Schematic created using CircuitLab

A more normal requirement is +/-300mV, but that still can't be met easily by a few discrete parts.

A considerably relaxed requirement is +/-300mV or +/-100mA max with normal operation not expected during transient conditions and a reset may be required to restore normal operation. In particular, analog accuracy and functionality is often disrupted by this sort of thing.

In such a case you may be able to use a simple series resistor such as 100K (using the internal protection network on the chip). Care should be taken that the current through the resistor does not raise the supply voltage when it is positive.

Pay attention to Russell's cautions-- ignoring specs is a good way to get into serious trouble. Keeping the I/O voltages of all chips exactly within the supply rails under transient conditions is usually just about impossible though, practically speaking.

Early CMOS chips had very poor latchup immunity and a small spike below or above the supply rails would cause them to fail spectacularly. These days the giant parasitic SCR that lives within most non-military CMOS chips (SOS is an exception) has mostly been tamed and it tends to cause more subtle misbehavior unless you really whack them with a high current transient of many tens of mA. Still for space applications we have to consider such major single event upsets and recover from them.

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  • \$\begingroup\$ thanks, but allow me one question about your design, won't buffer output lower than 1-logic level needed? Also exceed the maximum current allowed (some pins of my MCU are 4mA, few of them support a bit more)? I'm not being able to see the voltage at R3 input, will it be 3V3? \$\endgroup\$ – Yolco Jun 17 '15 at 11:40
  • \$\begingroup\$ Normally a '1' for the buffer is minimum 0.7 * 3.3 = 2.3V. The clamp will give you about .6 + 2.5V = 3.1V, which is not a bad '1'. The buffer will give you 3.3V for your GPIO. \$\endgroup\$ – Spehro Pefhany Jun 17 '15 at 12:12

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