Digital Input Clamp Circuit Protection

Question

To be able to connect some peripheral to digital input, I'm designing the circuit protection to avoid any possible failure due to over/under-voltage issue. So, I will add a clamp protection circuit. The requirements I need to accomplish are:

• Power Source (Vcc): 3V3
• Max Voltage: 3V9 (3V3 + 0V6)
• Min Voltage: -0V3 (GND - 0V3)
• Max Logic input current: +/- 300nA

The circuit is next:

R1000 is added to limit the current to 10mA. R1001 is added to limit the input current below 300nA.

My doubts are:

• Might the circuit be modified in case it need to support up to 30V input?
• Which would be the best option for both diodes (Forward voltage, breakdown voltage, forward current, etc)?
• As digital inputs may need to produce a rising interrupt, will be better to add a schottky instead of a zener on D1000?

Answer 1

This is all you need:

^{simulate this circuit – Schematic created using CircuitLab}

this also eliminates the problem that a high voltage at the input will lift-up your local VCC.

When input < -0.6 V D1 will conduct and limit GPIO to -0.6 V, R2 limits the current, your GPIO input will be able to handle this (it also has input protection diodes !)

When input > -0.6 V but < 3.9 V D1 does nothing, GPIO also happy

When input > 3.9 V D1 will conduct, R2 will limit any current, GPIO input will be happy.

Someone complained this would not work but was too lazy to explain why but I figured it out myself:

Apparently I overlooked that 3.9 V zenerdiodes leak a lot in reverse so I lowered R1 to 10 kohm. If that still doesn't fix it than you could replace the zenerdiode with 4 to 5 standard diodes in series, see 2nd schematic.

Answer 2

General guidelines being given are generally OK

BUT

You MUST NOT exceed Vdd with any sort of drive capability.
The 3V9 you quote is an ABSOLUTE MAXIMUM value and your controller may well go gaga if you apply that during operation. Look at data sheet in 'typical operating conditions' section and see what limits there are. In a very few datasheets, probably written by marketing men or the office cleaner, they may say 0.2V or 0.3V outside rails is OK BUT more than 0.small is dangerous. Real designers [tm] say 0.0V outside rails in their data sheets.
Experience suggests that the 1M you showed for R1001 is a good idea if you MUST have Vin > Vdd. Still not marvellous but will more often be more liable to be reliable.

Some people argue long and hard that body diode conduction at small currents during operation is OK. Listen to them if you don't care about commercial levels of reliability.

Current in body diodes usually flows into IC substrate and may end up in nodes not usually powered an can trigger spurious FET action where no FET usually exists and can noise up ADCS. These effects are insidious and unpredictable and may be fatal to design reliability. Many "RAD hard" parts (you pay for them in gold) and some others may be designed to specifically target these issues but the large majority are not.

IF your diode clamps allow input voltage to always be
>= Vin_high_min and
<= Vdd_min_actual
(and equivalent for Vin low) for all legal and likely Vin high (and low) during operation then you will be better off than dicing with Murphy.

Answer 3

The requirement for maximum +/-300nA input current means that you have to clamp the input voltage to within about +/-100mV of the supply rails (depending on temperature range). If you really need this spec (for example to ensure normal operation during input spikes) then you'll need better clamping than a few resistors and diodes can provide.

I suggest a clamping the inputs with a series resistor and diodes to ground and a shunt regulator such as TL431, then a series resistor to a CMOS buffer. The buffer will not exceed the supply voltages at its output and most can withstand several mA at the input without major malfunctions (they may draw more supply current but they won't latch up).

^{simulate this circuit – Schematic created using CircuitLab}

A more normal requirement is +/-300mV, but that still can't be met easily by a few discrete parts.

A considerably relaxed requirement is +/-300mV or +/-100mA max with normal operation not expected during transient conditions and a reset may be required to restore normal operation. In particular, analog accuracy and functionality is often disrupted by this sort of thing.

In such a case you may be able to use a simple series resistor such as 100K (using the internal protection network on the chip). Care should be taken that the current through the resistor does not raise the supply voltage when it is positive.

Pay attention to Russell's cautions-- ignoring specs is a good way to get into serious trouble. Keeping the I/O voltages of all chips exactly within the supply rails under transient conditions is usually just about impossible though, practically speaking.

Early CMOS chips had very poor latchup immunity and a small spike below or above the supply rails would cause them to fail spectacularly. These days the giant parasitic SCR that lives within most non-military CMOS chips (SOS is an exception) has mostly been tamed and it tends to cause more subtle misbehavior unless you really whack them with a high current transient of many tens of mA. Still for space applications we have to consider such major single event upsets and recover from them.