I am working on a MIPS CPU for an FPGA - this is mostly a personal project to understand FPGA's.
I have a 5 stage pipeline CPU implementation working correctly when run on iSim, however when I run it directly on the hardware (Spartan 6) I get a different result.
The test program I have is simple:
load 0x128 into reg nop* load 0x160 into reg nop* add reg to reg assert "finished" flag
when I run this in iSim, I get the correct result in reg (0x288) however, when I run the program on the FPGA I get the result 0x3b0 - it appears that the final instruction is running multiple tiems
nop instructions are present to force a cache miss during execution, and this is what causes the problem - without these the result is correct.
What I think is happening is that I assert a "stall" flag at the positive edge of the clock cycle - and something else that runs at the positive edge relies on the presence/absence of this flag. iSim by chance runs correctly (due to the arbitrary order in which it executes the simulation of always blocks) however the FPGA fails as the stall change is not available until the negative edge.
I have already scoured my verilog implementation to find where this is - and am still looking. My question is: how can I force iSim to expose this error?