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What's the difference between a CPLD and an FPGA?

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closed as off-topic by Leon Heller, PeterJ, Ricardo, Rev1.0, Nick Alexeev Jun 19 '15 at 19:26

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    \$\begingroup\$ CPLD uses product terms only (and one DFF per output pin); FPGA has internal configurable blocks of LUT, carry/shift, DFF, as well as more flexible routing, block RAM, and other specialized blocks like PLL or MAC. \$\endgroup\$ – MarkU Jun 17 '15 at 8:45
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    \$\begingroup\$ ...and normally CPLDs use non-volatile memory to store their configuration whereas FPGA use volatile memory (RAM), i.e. FPGAs have to be initialized each time after power-up. \$\endgroup\$ – Curd Jun 17 '15 at 10:16
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    \$\begingroup\$ Answer readily available using Google - question should be closed. \$\endgroup\$ – Leon Heller Jun 17 '15 at 10:53
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    \$\begingroup\$ @Leon Heller I dont know why you want to invoke other person to close this question. If you feel that this question should be close you are free to vote for closing but really its horrible to comment "question should be closed" and try to invoke other person to come along with you. If this question is liable to closed then first you should close the below question electronics.stackexchange.com/questions/1092/… \$\endgroup\$ – Sanjeev Kumar Jun 18 '15 at 15:13
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    \$\begingroup\$ @LeonHeller (et al), this very question also comes up as an answer to that Google search. (I got it as the second link, along with others that were actually useful.) \$\endgroup\$ – ilkkachu Feb 1 '17 at 18:45
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CPLDs are generally only used for replacing a relatively small amount of discrete logic. Namely, things like a bunch of address decoders and bus interface circuitry. CPLDs contain very little memory; genrally the number of flip-flops is of the same order of magnitude as I/O pins (i.e. a 32 macrocell CPLD has ~30 pins and ~30 flip-flops). The combinatorial logic in a CPLD is implemented on a programmable logic array, which generally is not useful at very high speeds. CPLDs are also usually flash-based or have internal flash memory, simplifying board design requirements and improving protection against reverse-engineering. CPLDs are also not built with 'bleeding edge' logic processes.

FPGAs are designed for very high performance computation and high bandwidth interfacing. Internally, they use a very different architecture than CPLDs. FPGAs have a lot more internal state (registers and block RAM) than they have I/O pins. Combinatorial logic is implemented on high speed lookup tables that can run to several hundred MHz. The LUTs and other components are interconnected with a high performance routing network. FPGAs also contain specialized hard cores that provide efficient implementations of various components. Block RAM and multipliers/DSP slices are very common. FPGAs can also contain ethernet MACs, hard processor cores, PCI express interfaces, and other specialized blocks. Multi-gigabit transcievers are also a common feature of high-end FPGAs that permit transfer of data at up to 50 Gbit/sec per pin pair. FPGAs generally do not contain any nonvolatile memory, so external flash memory is required to load the configuration. Encryption can be implemented to improve design security with a battery-backed key stored in the FPGA.

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Differences:

  1. Capacity - CPLD usually has less capacity of logic. The largest CPLD may be at a similar level of the smallest FPGA in the mainstream market.

  2. Storage of the image - CPLD can boot by itself while most of the FPGA need to fetch the configuration bitstream from non-volatile storage because they are SRAM based. This impacts the security of the system.

  3. Feature - CPLD only provides gates, or said, logic cells, that can do all kinds of logic algorithms. In addition, FPGA also embedded a lot of hard blocks such as BlockRAM, DSP, TEMAC, PCIe, MGT, microprocessor, etc to make a single chip of FPGA capable of building a integrated full featured system.

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    \$\begingroup\$ Regarding #3, it's worth mentioning that over the years as CPLDs have become more sophisticated the line between CPLDs and FPGAs has blurred. For instance, modern CPLDs are large enough to implement a microcontroller. It's to the point now where some chip families which were historically marketed as CPLDs are now being marked as FPGAs (the Altera Max family, for example) \$\endgroup\$ – David Gardner Jun 26 '15 at 3:45

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