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Currently I'm working on a C8051F120 MCU where External Interrupts can be defined in two ways:

  1. Edge sensitive (Falling)
  2. Level sensitive (low-level)

In level-sensitive interrupts as soon as the MCU detects a low level at the external pin it will execute the ISR which is the same as detecting a falling edge.

I know I'm wrong as both can't be the same. Hence I'm asking this question: what's the actual difference between the two, in their detection procedure or in the execution of the ISR?

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Its exactlly what is says.

If edge interrupt is set, the ISR will only get fired on falling/rising edge of a pulse. While if level sensitive interrupt (as you say) is set the ISR will get fired everytime there is a low-level/high-level signal on the corresponding pin.

In short, edge interrupt gets fired only on changing edges, while level interrupts gets fired as long as the pulse is low or high.

So if you have low-level interrupt set, MCU will keep executing the ISR as long as the pin is low.

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  • \$\begingroup\$ Thanks I got what I wanted..just one more clarification I need.. in case of low-level interrupts it will keep on executing ISR as long as signal is low..it will get out of ISR routine only when signal level goes high, right? \$\endgroup\$ – nkg2743 Jun 17 '15 at 9:48
  • \$\begingroup\$ @nkg2743 Yes, you are correct. \$\endgroup\$ – Golaž Jun 17 '15 at 9:50
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    \$\begingroup\$ I would rephrase the last sentence "it will get out of ISR routine only when signal level goes high" - because it is going out of the ISR but it is then starting the ISR again and again, instead of not leaving the ISR. \$\endgroup\$ – vsz Jun 17 '15 at 11:34
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A level sensitive interrupt and an edge sensitive interrupt are actually two quite different things. I'll try to give some general insights that might help you understand how other interrupts work too.

Let's assume that your CPU can execute code in two modes: normal mode, and interrupted mode. To go from normal mode to interrupt mode an interrupt, whatever it is, must happen, while to come back the IRET instruction must be executed. Let's also assume that if an interrupt happens while in interrupt mode it gets somehow saved but it is not immediately serviced, i.e. when in interrupt mode the CPU can not be interrupted.

So what is an interrupt? I would say it is an event: something that happens, a timer overflows, a pin goes low, whatever. The CPU does something to respond to the event then resumes normal execution. What happens if an event occurs while another is being serviced? Usually a bit is set in some register and just after the IRET instruction the CPU is interrupted again, checks which bit is set and executes the correct interrupt service routine.

You might now see why level triggered and edge triggered are two different things: they are two different events. When your ISR on the level triggered interrupt is executed you probably clear the interrupt bit as first thing: if the level stays low the hardware immediately triggers another interrupt that will be serviced just when you are finished with this. In an edge triggered interrupt you need the pin to go high and then low again to trigger the interrupt once more.

I can't think of a meaningful example of when you would need a level triggered interrupt, edge triggered seems much more useful and what you'd usually need anyway.

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  • \$\begingroup\$ One example of a level-triggered interrupt might be a low battery warning, but I'm not sure if that's how it's usually implemented. \$\endgroup\$ – Greg d'Eon Jun 17 '15 at 13:11
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On many systems, interrupts may be divided into three categories--not just two; many systems only support two of the three, but there may be some difference as to which two they support.

An edge-triggered interrupt will cause the CPU to switch to interrupt mode any time interrupts are enabled, the interrupt line has been in the inactive state some time after the interrupt was last reset, and has been in the active state some time after that.

A "pure" level-triggered interrupt will cause the CPU to switch to interrupt mode any time interrupts are enabled and the interrupting signal is currently active.

A "pure" level-triggered interrupt will cause the CPU to switch to interrupt mode any time interrupts are enabled and the interrupting signal has been in its active state since it was last reset (if it was in its active state when reset, it may have simply stayed in that state).

A major advantage of level-triggered interrupts is that if while a device is being serviced for one reason, another reason emerges that would cause it to require attention (or another device using the same line requires attention), the CPU will keep revisitng the device until it is completely satisfied and has no cause to hold the reset line.

The primary disadvantages of level-triggered interrupts are that they often require that the CPU take explicit action to reset them (edge-triggered interrupts are often implicitly reset by the interrupt controller when the interrupt is dispatched), and that an interrupt which gets enabled when the CPU has no idea how to service it can lock up the system, since the CPU will do nothing except repeatedly invoke the interrupt handler because the device will continuously need (but never receive) attention.

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