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I have run a simulation of a Verilog code testbench. I ran it in ModelSim, but why the reading I got from just using the cursor on the waveform is different from the one in transcript window.

While in the cursor, the WDIG_OUT values is offset 1 step backwards, making the 111 wDIG_OUT to match with 2181 rANALOG_IN. (just like in the case of "a" here).

I cannot proceed to self-checking because there is an offset. Please help.

enter image description here

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That looks correct. The values in the transcript window are the signal levels 'leading in' to the clock edge. This constitutes an ideal setup time. With the cursor positioned directly on a clock edge, the values to the left side will be the 'inputs' and the values to the right side will be the 'outputs'. This represents an ideal propagation delay of zero, setup time of one clock period, and hold time of zero. You will have to delay the input by the propagation delay of the logic (in this case one clock cycle) if you have to directly compare it with the registered output.

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  • \$\begingroup\$ can you teach me or give me a clue how to get the value of the "previous input" so that I could compare it with the output. I am now in the process of making a "scoreboard" (don't know if i call it right. \$\endgroup\$ – Dragonald Valenciano Jun 18 '15 at 2:41
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    \$\begingroup\$ Just add an always block that will store the value of the signal in question on every clock edge of the corresponding clock, then use this stored value for comparison. \$\endgroup\$ – alex.forencich Jun 18 '15 at 2:44
  • \$\begingroup\$ thank you so much. now i know, nothing is wrong with my simulation. nothing to worry about the "discrepancy" in the data. \$\endgroup\$ – Dragonald Valenciano Jun 18 '15 at 3:11

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