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This document cites 60 DMIPS/mW for a Cortex M0, vs 31 DMIPS/mW for an M3. (The latter doesn't agree with the numbers in this document, which cite 1.25 DMIPS/MHz and 0.19 mW/MHz, giving 6.6 DMIPS/mW.)
Does anyone know how the M0 performance/power compares to 8/16-bit controllers like AVR, PIC and MSP430? And what's the deal with the M3 figures?

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    \$\begingroup\$ @frederico this is a very loaded question and there is no easy answer. Since, my experience is the other stuff determines the performance.. Things like prefetch capabilities, bus speeds, number of peripherals hanging down a bus, flash access speeds etc. etc. If you profile a system well you almost always see getting the data in and out becomes the bottle neck. Well, if you detail your application, I would be happy to provide insights into what is the best route to choose the processor. \$\endgroup\$
    – Frank
    Jul 31 '11 at 6:30
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    \$\begingroup\$ @Frank: Doesn't the Dhrystone benchmark take things like prefetch and bus speed implicitely into account? I particularly would like to have the contradicting NXP M3 figures cleared up. Can't give you details about app, because details don't exist yet :-) \$\endgroup\$ Jul 31 '11 at 9:13
  • \$\begingroup\$ @Frederico, I consider myself below average engineer, certainly not an architect. I don't trust any benchmark out there since the data is almost always massaged. For eg if you have a high speed data sink that requires you to push data in and out and in the mean time you need to access to memory and other peripherals, this case bus gets in the way. These processors are designed it for average use cases. If you are doing soft decoding of certain data that requires several memory read/write and the data path may overflow or starve. This usually ends in sleepless nights for software guys. \$\endgroup\$
    – Frank
    Jul 31 '11 at 11:23
  • \$\begingroup\$ These days the Dhrystone is a fun toy but doesnt tell you much. Benchmarks in general do not tell you much at all. You have to take your application and run it. The compiler you choose not changing any code or hardware can make a several times performance difference plus or minus, so this is all very difficult. You can make benchmarks that make the numbers show whatever you want. \$\endgroup\$
    – old_timer
    Oct 14 '11 at 4:40
  • \$\begingroup\$ The ARM is going to run circles around the rest for pure performance (at a similar size and similar price, not necessarily power). I dont think even an 8051 is as slow as a PIC, can you fathom the number of lost clocks to do anything useful? Using asm, then folks use C and it becomes unbearable to watch. The msp430, you probably want it for apps where you turn it off, it wakes up once in a blue moon does a couple of things then goes to sleep, like a TV remote control or something like that. \$\endgroup\$
    – old_timer
    Oct 14 '11 at 4:46
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Here are a couple of pointers that I can provide. The specifications that NXP is providing is for their entire chip (core, memory, peripherals). The specification that ARM provides is based on just the core. As the numbers are derived differently it's really hard to do the comparison.

So, I propose we step back and look at two devices. An NXP M0 based MCU, and an MXP M3 based MCU.

For the M0 based MCU let's look at the LPC1111. When this MCU is executing an busy idle loop it will consume 3mA of current at 12MHz clock rate. This yields 250uA/MHz, which at 3.3V is 825uW/MHz.

For the M3 based MCU let's look at the LPC1311. When this MCU is executing the same busy idle loop it will consume 4mA of current at 12MHz. Yielding 333.3uA/MHz, which is 1.1mW/MHz.

If we look at a MSP430C1101 MCU (16-bit) we'll see it's going to use 240uA at 1MHz when the voltage is 3V. This yields 720uW/MHz.

Next, let's turn to the ATMega328 (used in Arduino Uno). We see 200uA used at 1MHz with a voltage of 2V. This yields 400uA/MHz.

It should also be noted that the MSP430 and AVR are spec'ed differently. Their power consumption is given at 1MHz, where as the M0 and M3 are given at 12MHz. This means the M0 and M3 have inefficiencies of scaling up to 12MHz baked into their numbers.

These values are all active current consumption numbers. If you look at the current consumption when the device is in a sleep state you see orders of magnitude less power being used. The advantage that the 32bit M0 provides is that it can get a lot more work done in less time than the 8 and 16 bit MCU. This means for a given workload it will spend a lot more time in a sleep state. The M0 in the hands of a good engineer will often times get far better power efficiency than an 8-bit MCU in the hands of a less skilled engineer despite the differences in active power consumption.

From my experience the M0 is so close to 16 and 8 bit active power consumption that you can make up for a lot of the differences in application. Also, many times the power consumption of everything you have hanging off of the MCU dwarfs the MCU. So, for a lot of applications tackling the efficiency of the MCU isn't the most important thing.

I hope that helps. It is a long way of saying that power consumption is a bit worse, but you get a lot more done with those clock cycles than other chips would. So, it really depends on your application.

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    \$\begingroup\$ Re your first paragraph: if the ARM figures are just about the core then they should be higher than the NXP figures, which include peripherals power. But they're lower. I can't explain it either. \$\endgroup\$
    – stevenvh
    Oct 14 '11 at 14:17
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    \$\begingroup\$ Also, you should compare the controllers at equal voltages. If you run the LPC1111 at 3V like the MSP430 their power consumption is very close. Not bad for the NXP ARM; the MSP430 is known for its low power. \$\endgroup\$
    – stevenvh
    Oct 14 '11 at 14:22
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    \$\begingroup\$ one big problem that I have had with ARM cortex devices compared to the MSP430 is that the ARM devices can burn a lot of processor cycles getting back to the running state from their low power mode. The RAM data is lost and has to be re-created/initialised (apart from the battery backed SRAM) the PLL and clock system has to be restarted. The MSP just resumes from the next instruction with all of the RAM intact from when it went to sleep. If your process involves frequent transitions between active and sleep modes then the ARM will lose. \$\endgroup\$
    – uɐɪ
    Mar 6 '13 at 14:03
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Comparing 12MHz to 1MHz is biased - higher clock rates require less current per MHz. For example latest MSP430's can go as low as 80-120uA per MHz with 8/16MHz in active mode.

It is worth mentioning that properly written code keeps active mode of MCU below 1% (or even 0.1%) of time, so power modes make a lot difference here.

In real life MSP430's are hard to beat (I'm not a TI emploee) due to very useful low power states where other MCUs take longer to wake up or do not keep RAM contents, which is ridiculous.

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