I believe the circuit shown below will accomplish what you need. One I2C device is shown, along with two SPI devices. The circuit can be easily expanded to any number of I2C or SPI devices. The additional logic gates required are shared between all devices; there are no logic gates needed per device thus keeping parts count down. Only one extra lead is needed above the maximum four (plus SPI chip selects) needed for the standard I2C/SPI interfaces.
On the PIC18F25K80, SCL (I2C clock) and SCLK (SPI clock) are on the same pin, and SDA (I2C data) and SDI (SPI data in) are on the same pin. SDO (SPI data out) is on a pin by itself.
There are two issues: one is to disable the I2C device(s) when an SPI device is selected (and conversely, to disable the output(s) line of the SPI device(s) when they are not selected); and secondly to deal with the issue of pull-ups on the I2C lines when the SPI SDO lead is driving the SDA/SDI line on the microcontroller.
To handle the first issue, all of the SPI chip selects are AND'ed together. I am showing a 74HCT21 four-input AND with two inputs unused; this could be expanded to any number of chip selects.
If any chip select is 0, then the output of the AND gate is 0, which disables the analog switch, so the SCL clock from the microcontroller is disabled from reaching the I2C device(s). If all chip selects are 1, then the output of the AND gate is 1, enabling the analog switch, so the SCL clock is passed bi-directionally between the microcontroller and the I2C device(s).
For the second issue, a pullup is provided on the SDA pins per the I2C spec. Of course this puts a pullup on the SDA/SDI pin of the microcontroller as well. Since SPI devices are not setup to drive against a pullup, I added a 74HCT07 open-collector buffer to take care of this issue.
The buffer is preceded by an OR gate, with one input from the same lead that enables/disables the I2C clock. So that when the I2C interface is enabled, the OR gate is always asserted, keeping the open-collector output of the buffer high.