There are two different ways that chips on a motherboard communicate with each other: synchronous communication and asynchronous communication.
Most motherboards have a clock generator that controls a global clock signal that synchronizes the memory, the CPU, and a few other chips.
A so-called "DDR3-1333 memory" is tested to work up to 166.7 Mhz.
When it is plugged into a motherboard running at with a 100 MHz memory clock, that memory actually runs at 100 Mhz and works fine with a CPU with a 100 MHz memory clock.
(That memory does not have an internal 166.7 MHz clock).
If someone were to change the global clock frequency (most modern motherboards allow a person to easily change the frequency with a BIOS setting), then the memory would actually run at whatever frequency the clock generator sends to the memory chip.
It reminds me of a 130 mph automobile tires. They don't actually operate at 130 mph all the time. Something else controls the actual speed the tire moves, and the tire is designed to handle any speed requested of it, as long as that speed is no more than 130 mph.
For a variety of reasons, many devices on a typical motherboard run at a clock rate different from the metronome-like motherboard global clock signal.
Some of those devices, such as many modern CPUs, have an internal oscillator phase-locked to oscillate at some frequency that is a fixed ratio of small integers relative to the global motherboard clock signal.
Other of those devices, like the real-time clock chip, have their own crystal oscillator completely independent of the crystal oscillator attached to the clock generator.
(The ratio of their frequencies is often not a rational number, and sometimes slowly drifts).
While some researchers have built Clockless CPUs, pretty much all commercial CPUs are either completely synchronous, or
globally asynchronous locally synchronous (GALS).
When two devices with different oscillators (or two different clock domains on a GALS chip) need to transfer data to each other,
my understanding is that the 3 most popular techniques for clock domain crossing are:
- The data source sends a metronome-like "bus clock" that is less than half the clock rate of clock used by the destination (either the actual clock of the data source, if it is slow enough, or some slower signal derived from the clock of the data source) that tells the destination when to grab the data on the data lines. The destination registers the "bus clock" and the data lines, and accepts the new data on the agreed-upon edge of the clock signal. The data source holds the data lines constant before and after that "clock" edge, long enough that, no matter what the relative clock rate of the source and the destination, the correct data is latched.
- The data source uses gray code for data passing between clock domains so that no matter when the destination grabs the data (just before, during, or just after a change), the destination sees valid data.
- The data source uses some asynchronous communication protocol
that generally sets data on some wires, then sets some wire that indicates the data is ready. The data source holds those data lines constant until it receives a signal from the receiver that indicates the receiver has received that data and is ready for the next.