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I'm developing a circuit to act as an electronic load for bench testing power supplies. An earlier question about how to test this circuit received several very useful answers and can be found here: How to test op amp stability?. This question is about how to interpret my simulation and test results.

This is the circuit schematic as simulated and tested on the breadboard:

enter image description here

The plot produced by LTSpice indicates the circuit is quite stable. There is a 1mV overshoot on the 5V rise that resolves in one cycle. It can barely be seen without zooming in quite a bit.

enter image description here

This is a shot of the same test using the scope on the breadboarded circuit. The voltage rise is much smaller and the period is longer, but the test is the same; feeding a square wave into the non-inverting (+) input of the op-amp.

enter image description here

As you can see there is significant overshoot, perhaps 20%, then an exponential decay to a steady oscillation for the duration of the high signal, and there is some minor-ish overshoot on the fall. The height of the low signal is just the noise floor (about 8mv). This is the same as when the circuit is turned off.

This is what the breadboard build looks like:

enter image description here

The MOSFET is at the top on a heatsink, connected by the yellow, red, and black wires; gate, drain, and source, respectively. The red and black wires leading to the small proto-board are IN+ and IN- respectively, connected to the breadboard banana jacks to avoid power-level current through the breadboard. The power source being loaded in the test is a sealed lead-acid (SLA) battery, to avoid any instabilities in the power source itself. The silver jumper is where the square-wave is injected from my function generator. The resistor, diode etc. on the lower left is part of a manual (potentiometer-based) load level setting sub-circuit and is not connected.

My main question is: Why does LTSpice not predict this significant instability? It would be really handy if it did because then I could simulate my compensation network. As it stands I just have to plug in a bunch of different values and re-test.

My main hypothesis is that the gate capacitance of the IRF540N is not modeled in the SPICE model and I'm driving a ~2nF capacitive load that's not accounted for. I don't think this is quite right because I see capacitances in the model (http://www.irf.com/product-info/models/SPICE/irf540n.spi) that look to be the right order of magnitude.

Any way I can get the simulation to predict this instability so I can also tune in my compensation network values?

REPORT OF RESULTS:

Ok, it turned out that the LTspice model I was using for the LM358 op-amp was quite old and was not sophisticated enough to model the frequency response properly. Updating to a relatively recent one by National Semi did not predict the oscillation, but clearly showed the 20% overshoot, which gave me something to work with. I also changed the pulse peak voltage to match my breadboard test, which made the overshoot easier to see:

LTspice plot with better LM358N model

Based on that "feedback", I started with the unanimously recommended compensation method which I believe is an example of dominant pole compensation. I'm not sure if the gate resistor is part of that or a second compensation scheme, but it turned out to be critical for me. Here are the values I ended up with after a fair amount of trial and error:

Compensated schematic

This produced a very stable waveform, although I'd like to get the rise and fall a bit sharper if I could, to better test the frequency response of the power supplies I'll be testing with this load. I'll work on that a bit later.

Compensated LTspice plot

I then used the new values on the breadboard, and lo and behold I got this:

Compensated scope shot

I was pretty psyched about that :)

Especially since, to fit in the new components, I made the breadboard parasitics worse rather than better:

enter image description here

Anyway, this one ended happily, hope this helps others who find it on search. I know I would have torn out what little hair I have left trying to dial in these values by poking different components into the breadboard :)

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    \$\begingroup\$ LTSpice doesn't understand the inductors (aka wire jumpers) between your breadboard and the MOSFET. It also doesn't understand the likely tortuous path that 0V takes when using a breadboard. LTSpice WILL model gate capacitance and it's also worth noting that the source resistance will put a medium value resistor in series with that gate capacitance. \$\endgroup\$
    – Andy aka
    Jun 22, 2015 at 7:26
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    \$\begingroup\$ The IRF540 model I have used (PSpice) contains a bulk-gate cap of app. 2nF, a gate-source cap of 1.1nF and a gate-drain cap of app. 0.5nF. I suppose, the problems arise due to breadboard parasitic L and C influences. You should reduce the occupied area (shorter connection wires). \$\endgroup\$
    – LvW
    Jun 22, 2015 at 7:54
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    \$\begingroup\$ See my answer below (real opamp model and compensation network necessary). \$\endgroup\$
    – LvW
    Jun 22, 2015 at 9:20
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    \$\begingroup\$ ADd a 0.1uF low ESR cap with minimum possible series L from op amp Vcc to ground. It may look physically similar to the one connected to Vcc now but without the immense coupling loop and long breadboard tracks. It will probably plug in across the IC body from pin 8 to pin 4 and look ugly, but work semi-infinitely better. Then add the large electrolytic cap across the power supply rails where the Vcc line enters the breadboard power rail. If you can bring yourself to wire it, for now, in an ugly looking way from pin 4 to tin 8 as directly as possible that may help, ... \$\endgroup\$
    – Russell McMahon ♦
    Jun 22, 2015 at 20:10
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    \$\begingroup\$ ... but odds are the 0.1 uF you have there now (in place of the prior L + C) will help enough. If that hasn't helped or helped enough try a say 10 Ohm resistor from opamp output to FET gate. That's usually to stop things a bit more spurious and with less reason than the oscillation you are seeing. | It probably is well down the list of most relevant points but grounding both the inputs of the unused opamp is not a bad idea, (probably :-) - ie Murphy sometimes has other ideas). Report back ... . THEN you can look at the "what is wrong with my intended circuit Q&A that others are dealing with. \$\endgroup\$
    – Russell McMahon ♦
    Jun 22, 2015 at 20:15

3 Answers 3

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There are different models for the LM358 unit. PSpice simulations based on "LM358" result in a phase margin of app. 50...60 deg. But apparently, this is a very simple model.

However, when using the LM358/NS model the margin is slightly negative! This explains the observed instability during measurements. Hence, external stabilization of the feedback scheme is necessary.

Compensation: A compensation scheme (series connection R=500...1000 Ohms and C=50...100nF) at the opamp output node provides a phase margin of app. 50 deg. (simulation).

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  • \$\begingroup\$ This was an important help. I had been using an LM358 Spice model from 1989 that was far simpler than the LM358/NS model I found based on your pointer. I also reduced the injected square wave amplitude on the simulation to match my test level and between the two of them I am now clearly seeing the 20% overshoot with exponential decay on the rise. The oscillation doesn't appear on the simulation plot, but I'm fully satisfied for now with the overshoot, figuring if I can compensate that out neatly the oscillation is likely to go with it. I'll report on how it goes :) \$\endgroup\$
    – scanny
    Jun 23, 2015 at 20:16
  • \$\begingroup\$ Can you clarify the placement of the compensation components you mention? Are you thinking 1kΩ between V.sense node and inverting input and 100nF between op-amp output and inverting input? That would be a dominant-pole compensation I believe, wouldn't it? (just getting my compensation-type terms straight in my head :) \$\endgroup\$
    – scanny
    Jun 23, 2015 at 20:23
  • \$\begingroup\$ Thanks @LvW, this turned out to be the problem. Once I got the updated model in there it set me on the path to success. You get the green checkmark :) \$\endgroup\$
    – scanny
    Jun 24, 2015 at 7:00
  • \$\begingroup\$ Scanny, with the feedback capacitor you have now changed the opamp into an intergator (lowpass with a very small corner frequency). Of course, this stabilizes the whole circuit because bandwidth is reduced drastically - with the consequence of a bad pulse response (rise time increased). In control systems this method is called "stabilization to death". If you can live with it - fine. If not, you must try a somewhat more "tricky" compensation. \$\endgroup\$
    – LvW
    Jun 24, 2015 at 7:29
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    \$\begingroup\$ As I have told you in my detailed answer: R-C Series connection between opamp output and ground (0.5...1 kOhm and 50...100nF). \$\endgroup\$
    – LvW
    Jun 24, 2015 at 20:44
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The LTSpice simulation cannot account for circuit items that you have not entered: in this case, your breadboard wiring which is adding a filter (a RLC filter at that).

What you are seeing is Step response when you start driving the (almost) square wave into the amplifier. At the point where you initially pulse the input (having been held quiet for a significant amount of time) you are seeing damped response transients (apparent on the first few switching cycles) and then becomes closer to what you expected to see.

Although the FET is probably a low enough capacitance for the amplifier to drive, it is normal practice to decouple the gate capacitance through a resistor. This will form a low pass filter at the gate of the FET, so there is a trade-off of circuit response to amplifier ringing / overshoot, which is what you see once the initial step response has disappeared. There is also a pole from the inverting input to circuit reference (ground), and it is common to see a small capacitor in the feedback loop of about the same capacitance to compensate for this.

The value you should use is circuit layout dependent, but in this case I would start with about 100pF (on a properly laid out PCB this value would be more like 5pF to 10pF).

On amplifier ringing, there may be graphs in the datasheet that shows overshoot / undershoot vs. various capacitive loads. This is quite common in modern amplifier datasheets.

HTH

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I would not have applied such a scheme. This scheme is easily converted into a stable. Between the output and the gate of the transistor put resistor R1 = 1kOhm. Between the source of the transistor and the inverting input of the operational amplifier put a resistor R2 = 10kOhm. Between the output and the inverting input of the operational amplifier put a capacitor C1 = 1000pF.

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  • \$\begingroup\$ Thanks Alexander, these values were a good starting point and then I tuned them in from there :) \$\endgroup\$
    – scanny
    Jun 24, 2015 at 7:02

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