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In VHDL rising_edge is used to detect signal transition from logic zero to logic one. In almost every vhdl sample codes that I referred rising_edge is only used to detect logic zero to logic one transition of clock input.

Why it is recommended only for reference clock? Why can't we used this syntax to check logic zero to logic one transition of any other input or signals inside the program?

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  • \$\begingroup\$ See stackoverflow.com/questions/19879960/… \$\endgroup\$ – efox29 Jun 22 '15 at 10:57
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    \$\begingroup\$ Because synthesis tools look out for this pattern and translate it into the clock signal for a FF or register. You CAN use it for other purposes - the direction detector of a quadrature encoder for example - but that's pretty rare. \$\endgroup\$ – Brian Drummond Jun 22 '15 at 13:30
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    \$\begingroup\$ In extension to Brian's answer: You need some kind of signal history to detect a level change. This history can only be implemented by a register. A register needs a clock, but synthesis won't know with clock it should use. So it's not synthezisable. \$\endgroup\$ – Paebbels Jun 22 '15 at 17:37
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It comes back to draw the picture of what you proposed and then think about the implications.

Rising_edge has a special meaning. It designates the signal that connects to the clock pin of a flip-flop.

First consider signals that come from the output of regular logic. These are not suitable as clocks because they can glitch. In old board designs, we were able to remove glitches by creating logic with redundant terms, however, in FPGAs and ASICs we generally do not know if the target implementation will glitch or not. In addition, synthesis tools work hard to remove redundant logic - yes we can stop them from doing that, but no it is not fun. In addition, clocks generated off of logic have poor timing characteristics (delays, skew, ...). The old board designs were slow, so this wasn't too bad.

Now consider signals that come from the output of another flip-flop. Historically board designs did use these as clocks. We don't do this so much in ASIC and FPGA design. One reason is the design is considerably larger and the timing analysis becomes more challenging. Another reason is that we want to minimize the number of clock domains as any clock domain crossing must be done properly or it is problematic.

Generally in ASIC and FPGA designs, we try to minimize the number of clock domains. We try to keep good skew control of the clocks we do have - hence, we do not gate (add logic including inverters) to the clocks unless we are using a methodology that supports this.

In an FPGA, generally this means we are using a clock wizard or instantiating a vendors clock block. Those that know me may be giggling at that as my usual answer is write the code, wizards are evil (because the lock you into a particular vendor).

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