# What is the difference in assigning output before end process and after end process in VHDL

I have written a code to check the difference in assigning output before "end process" and after "end process" in VHDL. And the results of the simulation I have posted with it. What I found is assigning output 1:After "end process" there is no delay, output port is reflected with change in variable. 2:Before "end process" there is a pulse delay. but I'm not able to conclude it.

entity signal_delay is
port (clock_50M: in Std_logic;
r: in std_logic;
r_delay1, r_delay2: out std_logic);
end signal_delay;

signal r_1,r_2: std_logic;

begin
process(clock_50M)
begin
if ( clock_50M='1') then
r_1<= r;
r_2<=r_1;
end if ;
end process;

r_delay1<=r_1;
r_delay2<= r_2;



----case:2-------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity signal_delay is
port (clock_50M: in Std_logic;
r: in std_logic;
r_delay1, r_delay2: out std_logic);
end signal_delay;

signal r_1,r_2: std_logic;

begin
process(clock_50M)
begin
if (clock_50M 'event and clock_50M='1') then
r_1<= r;
r_2<=r_1;
end if ;
r_delay1<=r_1;
r_delay2<= r_2;
end process;


• It would be nice if the code was formatted a little! – copper.hat Jun 23 '15 at 6:20

In a sequential process the signal is assigned with the next event. If it is not in a clocked process the signal is assigned immediately.

But another thing is you have this block in your VHDL description:

process(clock_50M)
begin
if (clock_50M 'event and clock_50M='1') then
r_1<= r;
r_2<=r_1;
end if ;
r_delay1<=r_1;
r_delay2<= r_2;
end process;


This is not synthesised in a way you want.

1. You should put the r_delay1 <= r_1; and r_delay2 <= r_2; inside the if to determine on which clock edge it should happen. There are no Flip Flops reacting to both.

2. Do not use clock_50M 'event and clock_50M='1' use rising_edge(clock_50M) it is more readable