Currently looking into the specifications of the CD4015BC static shift register, I came across a couple of specs for which I have some questions:
1) The clock rise and fall times should be below 15 us, what happens with clock pulses that have longer rise times? Does the registers shift well? Or does it's behavior becomes unreliable?
2) There is a spec about minimum data set-up time (30us max for VDD=15V), what is meant with this spec please?
3) I don't find anything about the maximum output current on the output pins. What is mentioned is: "High level output current: Typical -8.8mA, minimal -3.0 mA" without specifying any load resistance...
Thanks for helping out with these.
(I am currently looking into a design which uses this kind of register in a cyclic way: at startup it clocks in a couple of random bits and then the output of the last register is fed back into the first input. Works well, the bits that were clocked in are cycling through the registers. But when changing the clock source from time to time, the bits that were clocked in originally, are gradually disappearing, all bits become zero... I suspect slow rise time of input clock to be the cause..)