Currently looking into the specifications of the CD4015BC static shift register, I came across a couple of specs for which I have some questions:

1) The clock rise and fall times should be below 15 us, what happens with clock pulses that have longer rise times? Does the registers shift well? Or does it's behavior becomes unreliable?

2) There is a spec about minimum data set-up time (30us max for VDD=15V), what is meant with this spec please?

3) I don't find anything about the maximum output current on the output pins. What is mentioned is: "High level output current: Typical -8.8mA, minimal -3.0 mA" without specifying any load resistance...

Thanks for helping out with these.

(I am currently looking into a design which uses this kind of register in a cyclic way: at startup it clocks in a couple of random bits and then the output of the last register is fed back into the first input. Works well, the bits that were clocked in are cycling through the registers. But when changing the clock source from time to time, the bits that were clocked in originally, are gradually disappearing, all bits become zero... I suspect slow rise time of input clock to be the cause..)

  • \$\begingroup\$ Is the rise time of your clock really greater than 15us? \$\endgroup\$ – Roger Rowland Jun 24 '15 at 7:42
  • \$\begingroup\$ yes, certain clocks that are used go for a tr of 20 us \$\endgroup\$ – pascalm Jun 24 '15 at 7:50
  • \$\begingroup\$ Use a schmitt clock buffer for your seemingly analogue clock signal. \$\endgroup\$ – Andy aka Jun 24 '15 at 8:41
  • \$\begingroup\$ ok, thanks, this is also my intention of doing. but i am also interested in a couple of issues regarding the specs, does anyone has any answers to those please? thanks \$\endgroup\$ – pascalm Jun 24 '15 at 8:44

The clock rise and fall times are due to (probably) 2 specific requirements.

  1. This is a CMOS device, and slow inputs on these devices cause significant self-heating due to the input stage conducting in class A while the input is in the indeterminate region. It is normal to see a maximum rise and fall time for CMOS devices.

  2. The clock input on the latch probably needs a transition no slower than this to attain properly deterministic operation.

Setup time. This is the amount of time that a data input must remain stable in a valid state (either high or low) before a clock transition. If this time is not met, the contents of the register will be indeterminate.

A decent reference for this may be found here

Output current. This is the maximum and minimum current available, and is defined by the resistance of the output stage. The load resistance you may use is defined by this, not the other way around.

Without a proper schematic, I cannot comment on why all the bits eventually become zero.

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  • \$\begingroup\$ ok, thanks, this was very helpful. i would like to vote your answer up, but lack 1 point for doing so;) \$\endgroup\$ – pascalm Jun 25 '15 at 7:25
  • \$\begingroup\$ so, for the good understanding, concerning maximum output current, if I short an output of the device, I will get about the current as indicated in the specs (typical,minimal)? \$\endgroup\$ – pascalm Jun 29 '15 at 7:26

The schematics of the circuit involved can be found here:[link]http://musicthing.co.uk/modular/wp-content/uploads/2012/05/random_seq_schem_2-1_big.png. I've build this random sequence generator. Most users get quirky behavior when using what they call 'multed' clocks, these are clocks coming from a passive clock distribution patch point. I had the same issues and wanted to solve the problem. After a bit of measuring around, it seemed to be that these 'multed' clock signals have significant rise times. On the schematic one can see that these clocks pass through a comparator build with TL072. But it seems not fast enough.

With 'slow rising' input clocks (>1ms), the clock output at the tl072 has rise times of about 15us-20us, which could explain the quirky behavior. It would have been better I think to have used a faster comparator at the clock input circuitry instead I suppose, in order to get rid of this 'quirkyness'.

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