In Verilog if we use
we can trigger a module at both rising edge and falling edge. Is there any method to do the same in VHDL.
Explicitly check for both rising and falling clock edges within the process:
process (clk) begin if (clk'event and (clk = '1' or clk = '0')) then null; -- Do stuff. end if; end process;
Or using the respective functions:
process (clk) begin if (rising_edge(clk) or falling_edge(clk)) then null; -- Do stuff. end if; end process;
However, there are subtle differences between the two variants (e.g. https://stackoverflow.com/questions/15205202/clkevent-vs-rising-edge).
Also don't expect this to be synthesizable.
In VHDL, you can use a PROCESS statement to do things when an input signal changes. To trigger on both rising and falling edges, you would use both falling_edge() and rising_edge() functions along with an OR statement.
ENTITY example IS PORT( a, clk : IN BIT; b : OUT BIT); END example; ARCHITECTURE behavior OF example IS BEGIN PROCESS (clk) -- Whenever the clock signal changes.... BEGIN IF (rising_edge(clk) OR falling_edge(clk)) THEN -- do something END PROCESS; END behavior;