0
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In Verilog if we use

always@(clock)

we can trigger a module at both rising edge and falling edge. Is there any method to do the same in VHDL.

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1
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Explicitly check for both rising and falling clock edges within the process:

process (clk)
begin
  if (clk'event and (clk = '1' or clk = '0')) then
    null; -- Do stuff.
  end if;
end process;

Or using the respective functions:

process (clk)
begin
  if (rising_edge(clk) or falling_edge(clk)) then
    null; -- Do stuff.
  end if;
end process;

However, there are subtle differences between the two variants (e.g. https://stackoverflow.com/questions/15205202/clkevent-vs-rising-edge).
Also don't expect this to be synthesizable.

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0
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In VHDL, you can use a PROCESS statement to do things when an input signal changes. To trigger on both rising and falling edges, you would use both falling_edge() and rising_edge() functions along with an OR statement.

ie.

ENTITY example IS
PORT(
    a, clk : IN BIT;
    b : OUT BIT);
END example;

ARCHITECTURE behavior OF example IS
BEGIN
    PROCESS (clk) -- Whenever the clock signal changes....
    BEGIN
        IF (rising_edge(clk) OR falling_edge(clk)) THEN
            -- do something 
    END PROCESS;
END behavior;

source: http://www.sigasi.com/content/clock-edge-detection

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  • \$\begingroup\$ process(clk) does not trigger on both edges. Firstly it triggers the process on any signal change of clk. Secondly the simulation code has a flip flop like behavior, in synthesis is just logic. So you have a missmatch between simulation and synthesis. \$\endgroup\$ – Paebbels Jun 26 '15 at 7:14
  • \$\begingroup\$ But a signal change is usually an edge. Unless you are using U, X, L, H or Z for a clock signal ;) \$\endgroup\$ – Michael Jun 26 '15 at 10:55
  • \$\begingroup\$ Pebbles: You're right. I've only just learned the basics of VHDL, but the clk signal has more signal states than just 1 or 0. I'll edit the code above. \$\endgroup\$ – Tom Jun 26 '15 at 14:44

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