I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing a testbench for the CPU, I found that there is an initial delay of 1 cycle when reading from this ROM. Is this normal and is there a way to fix this? Would this delay even matter in my CPU?
Depending on how you configured the MegaWizard settings, this is expected. If the ROM is contained in a block RAM, there is always at least 1 cycle read latency. Basically you assert the address at
t=0, then on the next clock cycle (
t=1) the address is loaded into the address registers in the BRAM. The data then appears at the data output of the memory ready to be clocked in at
If you use an MLAB then the address inputs can be specified to not be registered which means the data is ready to be clocked in at
t=1 - but this can reduce the FMAX of the system - because you have removed the clock cycle of pipelining.
The latency may or may not be an issue depending on how you design your CPU. As it is a fixed latency - it will always be 1 cycle - then you can account for this in your CPU design by adding pipelining to the instruction and data fetching - e.g. fetch the next instruction while processing the current one.