I am trying to make a simple project which involves acquiring some data from the adc of atmega8 chip and then sending that data to UART. But I cannot figure out what would be the maximum limit of the input signal frequency for it to be a reliable signal acquisition. I am using 10bit adc but don't really mind a 8 bit precision. I should also factor in the time required to transfer my data over the serial port. The data sheet says

By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.

Does that mean the sampling is happening at 200kHz? This is all very confusing to me.


3 Answers 3


What is the ADC Clock?

The section that you are seeing is for the clock used for the ADC. This clock is not directly related to the max sampling frequency though. The clock is what is actually being fed to the ADC module which needs to be faster than your sampling so that it can handle some magic for you.

How does the Max clock relate to the max sampling frequency?

What the datasheet is saying is that in order to get 10 bit resolution your clock can not be any faster than 200 KHz. When your clock is at that speed, you will be able to sample your signal at 15,000 samples per second.

If you don't need all 10 bits of resolution then you can provide the ADC with a faster clock and you will get a faster sampling rate, but the datasheet is not clear as to how fast you can go and still get 8 bit resolution.

I would assume that the clock to sample rate ratio is fixed, so 200K/15K = 13.33 which means you can go as low as 50 KHz clock resulting in 3.75 kSPS.

Why a minimum clock to get a 10 bit sample?

The ADC module is doing a sample and hold in which the voltage is essentially held in a capacitor. If you slow the clock down too much, the voltage can start to bleed off of the capacitor before a complete sample is performed. This change in voltage makes it such that you can't get all 10 bits accurately.

So what does this all mean?

According the the Nyquist-Shannon sampling theorem your sampling frequency needs to be at least twice the maximum frequency in your signal. You can learn more about why by looking at this question: Puzzled by Nyquist frequency

So in order to get 10 bits of resolution, the max your signal can be is 7.5 KHz, but if you need to sample a signal faster than that, you can, but the datasheet does not mention how high you can go or how much it hurts your resolution.

  • 2
    \$\begingroup\$ It takes 14 clock cycles to take a measurement with its particular ADC module in free-running mode (Fig. 101 in datasheet). The max. ADC clock is 1MHz (3LSB or 3/2^8=1.2% error), giving 71428 SPS, and 35714 Hz. \$\endgroup\$
    – tyblu
    Aug 5, 2011 at 2:57
  • \$\begingroup\$ @tyblu - That should really be an answer, especially if you improved it by providing a reference for your claim that the maximum ADC clock is 1MHz. \$\endgroup\$ Aug 5, 2011 at 3:31

I think you'll find the following article very useful, it describes the effect of higher sampling rate (higher than the manufacturer recommendation) to the ADC resolution in AVR



One line in the data sheet, in big bold letters says:

Up to 15 kSPS at Maximum Resolution

So 15,000 samples per second.

As you need twice as many samples as your frequency to sample accurately*, you are limited to 7.5KHz.

* According to the Nyquist theory - Thanks guys.

  • \$\begingroup\$ could it be Nyquist? \$\endgroup\$
    – NickHalden
    Aug 4, 2011 at 20:00
  • \$\begingroup\$ Nyquist frequency, I believe \$\endgroup\$
    – pfyon
    Aug 4, 2011 at 20:01
  • \$\begingroup\$ en.wikipedia.org/wiki/Nyquist%E2%80%93Shannon_sampling_theorem \$\endgroup\$
    – Kellenjb
    Aug 4, 2011 at 20:03
  • \$\begingroup\$ so to add to that you are limited to 7.5 khz with a brick wall filter - which does not exist, so you could cascade two single pole active op-amp filters giving you 40 db per decade (100 th less). So for a given resolution of 19 mV (8 bit a/d) and input range of 0-5 V you need a 48 dB reduction at fnygquist. So to get that you will probably need to set your fc at 675 hz of your anti alais filter circuit \$\endgroup\$ Aug 4, 2011 at 20:41
  • 1
    \$\begingroup\$ Nyquist doesn't say that you can't accurately sample signals above FS/2, what is says is that you can't unambiguously do so. Once you have the possibility of energy in that range, you can't distinguish it from energy at a complementary frequency from the sample rate. The actual maximum frequency (more like a roll-off) that can be sampled is determined by the analog bandwidth of the sampler, rather than the sample rate. \$\endgroup\$ Aug 5, 2011 at 15:57

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