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Below is the device utilization summary for the design(Zynq 7010) and the use of Slice LUTs exceeds the availabile number. Previously it was 82% and now it exceeds after adding a block of checksum code 4 times. Is there any tweek to merge LUTs and reduce its consumption or need to make manual optimization in the code?

Device Utilization Summarry

Below is the synthesis settings:

Synthesis settings

I have used the following settings for implementation to reduce some kind of resource utilization especially LUTs

Implementation settings

*I got some information from this website: Xilinx parameters

After using the above settings, the problem still persists. I am not sure about some settings, whether they are valid for Zynq or not. Any help?

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  • \$\begingroup\$ Do you use the four checksum blocks in parallel? \$\endgroup\$
    – TM90
    Commented Jul 1, 2015 at 14:13
  • \$\begingroup\$ @TM90: Yeah it is a parallel CRC checker module. \$\endgroup\$
    – Pradeep S
    Commented Jul 1, 2015 at 14:18
  • \$\begingroup\$ Based on your data, your CRC checker module would take around 880 slice LUTs, which is enormous IMHO. I find the hierarchical netlist view in Vivado very helpful to identify the largest blocks in your design, blocks you should focus on making smaller. Playing with synthesis option will only get you so far. Beside, it is not unexpected to see a 90% utilization design fail routing, I always target 80% at most. \$\endgroup\$
    – Jonathan Drolet
    Commented Jul 1, 2015 at 15:26
  • \$\begingroup\$ The crc checker module is a small piece of code. I do not know why it takes that much resource or is there something else in the design which is causing this issue. I need to find it first. Is there any way to know the hierarchial netlist view in PlanAhead(14.3)? \$\endgroup\$
    – Pradeep S
    Commented Jul 1, 2015 at 15:53
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    \$\begingroup\$ Open the synthesized (or implemented) design and press "F6". Any reason not to use Vivado? If you trust Xilinx (and you can on that matter) it will yield much better design for the series-7. \$\endgroup\$
    – Jonathan Drolet
    Commented Jul 1, 2015 at 15:58

1 Answer 1

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Remove the register duplication, it increases the speed of your design and have very negative impact on the utilization of LUTs in your design.

Those are mainly for the designs that have high fanout and needs to duplicate some of the resources in order to meet the timing.

Also, look into your code and see if you can remove the reset from some of your logic, specially parts that can be packed into SLR or RAM, that is one of the common mistakes people make, removing the reset, will help Vivado to pack some of your logic into BRAM or SLR and you will see a significant decrease in the number of LUTs used.

If none of those works, maybe your design is just too big for the FPGA you are using!

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