Below is the device utilization summary for the design(Zynq 7010) and the use of Slice LUTs exceeds the availabile number. Previously it was 82% and now it exceeds after adding a block of checksum code 4 times. Is there any tweek to merge LUTs and reduce its consumption or need to make manual optimization in the code?
Below is the synthesis settings:
I have used the following settings for implementation to reduce some kind of resource utilization especially LUTs
*I got some information from this website: Xilinx parameters
After using the above settings, the problem still persists. I am not sure about some settings, whether they are valid for Zynq or not. Any help?