3
\$\begingroup\$

I am building a hobby project using a GSM module and would like to be able to switch between multiple SIM cards, in case one stops working or I have poor reception on one provider (the project will be quite inaccessible once deployed).

Would there be any issues doing this with a CPLD? I can supply the SIM cards with 3V always. I was thinking I could switch them on / off with MOSFETs and just multiplex the CLK, IO and RST connections for each SIM.

Would it be easy/possible given that the IO line needs to be bi-directional?

Would the propagation delay of the CLK be an issue at all?

Anything else that might prevent this from working?

I don't have any experience with CPLDs

\$\endgroup\$
  • 2
    \$\begingroup\$ ICs exist for this which may save you work: ti.com/lit/ds/symlink/txs02326a.pdf \$\endgroup\$ – pjc50 Jul 3 '15 at 10:56
  • \$\begingroup\$ Thanks, but I'm looking at using more than 2 SIM cards \$\endgroup\$ – user5077257 Jul 3 '15 at 11:28
  • \$\begingroup\$ Quick fix will be to use multiple ICs similar to one mentioned by @pjc50 since you say you are new to CPLD too \$\endgroup\$ – Umar Jul 3 '15 at 11:35
  • 2
    \$\begingroup\$ You could take the IC as a starting point. That datasheet has reminded me that there are two different SIM voltages: electronics.stackexchange.com/questions/35358/… - which makes it a huge pain to drive. You might be better off with high-speed bidirectional analog switches in the data and clock lines. \$\endgroup\$ – pjc50 Jul 3 '15 at 11:47
  • \$\begingroup\$ Thanks for the suggestion, pjc50! Multiplexers seem the way to go. \$\endgroup\$ – user5077257 Jul 3 '15 at 14:49
4
\$\begingroup\$

Would it be easy/possible given that the IO line needs to be bi-directional?

Possible? Yes. Easy? Not so. You would have to detect the direction within the CPLD and switch the pins between input and output accordingly. It is a lot easier to just use an analog multiplexer chip like the 74HC4051 and control the address bits from a CPLD or microprocessor.

Would the propagation delay of the CLK be an issue at all?

In practice there is no phase relationship between CLK and IO, so it is not an issue. CLK is only used to define the baud rate of the IO line and runs at a much higher speed than the duration on a bit over the IO line. The initial speed of the IO line is one bit per 372 clock ticks. Your GSM modem may negotiate a higher speed transfer later on but lag on the CLK will never be a problem.

Anything else that might prevent this from working?

If you want to switch the VCC of the SIM cards via the CPLD check the maximum current that the CPLD can drive. You may need an additional driver to provide enough power.

I don't have any experience with CPLDs

A good opportunity to start lerning how to use them. They're fun!

On the other hand if you want to finish your project fast it is probably easier to just use four analog multiplexers like the 74HC4051 and switch all signals in parallel from a microprocessor. All you need are 3 GPIO pins to control up to 8 SIM cards. You won't have to deal with different voltage levels that way either.

Oh, one last thing: In practice all SIM cards nowadays support 1.8V and 3V so you don't really have to follow the power up sequence of starting with 1.8V and then switching up to higher voltages. For a commercial project I would not recommend this, but for a hobby project I think it's fine to simplify here.

\$\endgroup\$
  • \$\begingroup\$ Thank you for the detailed answer, Nils. This is all very helpful. It sounds like analog multiplexers are the way to go in this instance! \$\endgroup\$ – user5077257 Jul 3 '15 at 14:48
  • \$\begingroup\$ Hypothetically, how would one resolve the issue of knowing if the SIM or GSM module is sending data on the IO line and then "forward" that bit? (in the case of using a CPLD) \$\endgroup\$ – user5077257 Jul 3 '15 at 14:58
  • 2
    \$\begingroup\$ @user5077257 The IO line is on high level while it is idle. Each byte starts with a low bit (the stop bit). To detect the direction you just wait until one side sends this start bit. Once this happens you know that exactly one byte will gets transmitted. You can route the received data to the output and keep doing so until the stop bits gets transferred (will always be high level). At this point you can switch back both sides to input and wait for the next start bit. As you can see it's not that difficult. \$\endgroup\$ – Nils Pipenbrinck Jul 3 '15 at 15:14
  • 1
    \$\begingroup\$ @user5077257 You need access to the CLK line to derive the baud rate from it. Otherwise you won't be able to count the transfered bits. You'll also have to keep an eye on the data-stream and look for PTS requests. These are used to negotiate different baud rates (aka CLK division ratios). \$\endgroup\$ – Nils Pipenbrinck Jul 3 '15 at 15:20
  • \$\begingroup\$ That's super interesting, thanks! A bit complex for now, especially given the possibility of variable baud rates, but very interesting! \$\endgroup\$ – user5077257 Jul 3 '15 at 17:13

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.