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As part of MIPS design we have something called as register file. It only has 32 registers each 32 bit which only makes 1024 bits or 128 bytes. I am not sure how to tell Quartus to instantiate this as a memory block with 2 read ports and 1 write port. The Dual Port RAM in Quartus seems to be having 2 read/write ports. It is not possible to have 2 read and 1 write port. How do I create a 2 read port + 1 write port memory using the memory blocks in Altera Quartus II?

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  • \$\begingroup\$ Can the write port share the same address bus as one of the read ports? (Or is write access mutually exclusive with read access on one port?) \$\endgroup\$ – Tom Carpenter Jul 3 '15 at 22:17
  • \$\begingroup\$ It is mutually exclusive \$\endgroup\$ – quantum231 Jul 4 '15 at 8:43
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There's a trick for doing this in Xilinx technologies : instantiate two memory blocks, with their Write ports tied together. (Each block is configured to have 1 read and 1 write port, independently addressable).

I can see no reason why the same pattern wouldn't work in Altera FPGAs. Last time I looked, their memory blocks had similar dual-port (just not 3-port!) capability.

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  • \$\begingroup\$ well that looks like a good idea, I will do that \$\endgroup\$ – quantum231 Jul 4 '15 at 8:44
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Given from the comments your design writes and reads at different times, you can actually use a True Dual Port RAM for this.

For one of the read ports, you would wire up port A so that it is say read-only (tie the write enable permanently to 0).

For the other read, and the write, these would both share the same port on the RAM. You would use a multiplexer on the address input which is controlled by the write enable signal - so basically when you perform a write, the multiplexer will select your write address and connect it to the address pins of the memory. When you are not doing a write, the read address will be connected to the memory allowing you to perform read operations. This should work because as you say you never need to write and read on that port in the same clock cycle.

If you need more clarification, I draw up a diagram to explain further.

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You can't, as far as I know, because there is only the logic for two ports in the hardwired parts.

Your options are:

  • delay loading the second operand until the next pipeline stage
  • delay writing the result if the currently decoded instruction has two register operands
  • implement the register file in LUTs.
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