1
\$\begingroup\$

I've looked my FPGA datasheet and found that there is no pull-up/down resistors on it's pins(just a pull-up but that need to be enabled). So, when I power up my circuit I've for a "big" amount of time all IO pins of my FPGA floating. Since I've found that floating IO may damage some device or create problems, I want to put some pullup/down resistors.

Can someone advance me if it's better a pullup or pulldown resistor with which value? I've found someone advice pullup but they in some case can slow signal, other advice pull down, same for resistor values.

My main questions is: Floating pins can create problems only on input pin of a device or also in output pins?(where input or output are always defined in the device)

\$\endgroup\$
  • \$\begingroup\$ You don't need any pullups or pulldowns on floating FPGA pins. These chips are made for this situation. \$\endgroup\$ – Paebbels Jul 4 '15 at 13:33
  • \$\begingroup\$ But the CMOS chips being connected to may not be. Pull up pull down depends on what you want default state of the pins to be for the connected device when output is disabled. I'd check the datasheet and think about that. Traditional values are 10k or 4.7k and prob a fee more but really anything in that range ought to work. \$\endgroup\$ – Some Hardware Guy Jul 4 '15 at 13:37
  • \$\begingroup\$ Floating signals cannot generally affect output pins - unless there's so much interference on them that the induced voltage exceeds the supply rails. \$\endgroup\$ – Brian Drummond Jul 4 '15 at 14:21
  • 1
    \$\begingroup\$ While reading the SelectIO User Guide for Spartan-6 FPGAs from Xilinx I found this: By default, the Xilinx ISE development tools automatically configure all unused I/O pins as input pins with individual internal pull-down resistors to GND. This default behavior is controlled by the UnusedPin BitGen option. \$\endgroup\$ – Paebbels Jul 6 '15 at 11:45
1
\$\begingroup\$

This answer was given by a member of Xilinx staff to the same question on the Xilinx forums:

In http://www.xilinx.com/support/documentation/user_guides/ug191.pdf, apge 18, the HSWAPEN pin if pulled to ground, will enable the weak pullups on all IO pins prior to configuration.

After configuration, a pin may be set to pull up, or pull down, or to remain floating (effectively tri-state) or be driven high or driven low, depending on the IO standard chosen. It does no harm to have pins float.

The default in the software is probably not something you would like to rely on. It is far better to design the IO to do what you want it to do and state it explicitly.

I believe the default is a weak pull down for unused pins, however.

The weak pull up and weak pull down may often be too weak: a resistor of the proper value is recommended if there is a standard that you are trying to meet, as opposed to relying on the weak internal pull up or down.

Austin
Austin Lesea
Principal Engineer
Xilinx San Jose

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.