I'm preparing for a test and I currently stuck with the following question.

We have a 6502 microprocessor. For the execution of an absolute jump the jump address with the address high byte (ADH) and the address low byte (ADL) are loaded into the program counter (PCH,PCL). The question is now, why cannot both address bytes be loaded into the PC, but instead the ADL has to be stored first in the data buffer?

  • \$\begingroup\$ did this test burrow its way through a wormhole from 1982? Quick, turn on the wireless and tell us if Adam Ant, Duran Duran or Boy George are playing... \$\endgroup\$ – Brian Drummond Jul 5 '15 at 10:44
  • \$\begingroup\$ @BrianDrummond :-D But beware that in 1982 the only wireless they had was FM radio (at least for listening to music)! \$\endgroup\$ – Lorenzo Donati -- Codidact.com Jul 5 '15 at 11:38
  • \$\begingroup\$ I'm terribly curious: do they really teach 6502 assembler and architecture these days? Is it the introduction for ARM CPUs perhaps (they are derived from 6502 IIRC)? This brings back memories! When I was a teenager in ~1984 I learned how to program in 6502 assembly on my old Apple//e reading nerdy magazines! Actually I also learned to program in its machine language (what a pain - only then you really appreciate assembly) :-) CALL -151 anyone? :-D \$\endgroup\$ – Lorenzo Donati -- Codidact.com Jul 5 '15 at 11:50
  • \$\begingroup\$ @LorenzoDonati You'd be shocked at what they still teach in engineering programs. In my undergrad, I saw plenty of linear power supply designs in class, but not once did I see a switching power supply even mentioned. In a similar vein, we did tons of BJT circuits and FETs were pretty much just an afterthought. And this is recent - I'm due to graduate at the end of this year. \$\endgroup\$ – Peter Jul 5 '15 at 19:09
  • \$\begingroup\$ @PeterK Shocking! Really! I only hope they teach you the right approach: if your teachers are good, you can learn it even studying "old" circuitry, even if it is "boring" and disconnected from current reality. Anyway get yourself a copy of The Art of Electronics (3rd edition) from Horowitz&Hill and do a parallel study. As I often say to my students: "You can always learn things despite your teachers!" :-D \$\endgroup\$ – Lorenzo Donati -- Codidact.com Jul 5 '15 at 22:25

The 6502 jump instruction is three bytes long:


It is not possible to load both bytes of the PC at the same time, since the 6502 is an 8-bit CPU and can fetch only one byte at a time.

Therefore, it is executed in three cycles, one for each byte. After the instruction has been decoded, the CPU knows it is a JMP instruction. The low byte of the destination address (ADRL) is fetched and then held over until the beginning of cycle 3, so that the original PC value (updated) can be used to fetch the high byte of the address (ADRH) in cycle 3.

At the beginning of cycle 3, a new memory fetch is started with the original PC to obtain the high byte of the new address. At the same time, the held value comprising ADRL is used to update the low byte of the PC.

At the end of cycle 3, the fetched value (ADRH) is used to update the high address of the PC. This completes the jump instruction, since the next instruction will be fetched from the new PC location.

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  • \$\begingroup\$ This explanation is not correct; after PCL has been changed in cycle 2, the ADRH byte would not be fetched from the correct address in cycle 3. \$\endgroup\$ – CL. Jul 5 '15 at 10:53
  • \$\begingroup\$ @CL I see what you're getting at, but I also find it hard to believe there would be a separate 16-bit cache just for this one instruction. I'll see if I can find a block diagram of the CPU. IF you have a definitive answer, go ahead and post it. \$\endgroup\$ – tcrosley Jul 5 '15 at 11:01
  • \$\begingroup\$ Either the old or the new PC value must be buffered. The question asked why ADRL is stored in the data buffer. \$\endgroup\$ – CL. Jul 5 '15 at 11:04
  • \$\begingroup\$ You're both close to the correct answer, and I've taken the liberty of editing your wording in order to make the details clear. \$\endgroup\$ – Dave Tweed Jul 5 '15 at 11:22
  • \$\begingroup\$ @DaveTweed I modified your answer a little bit also, I finally found the cycle by cycle detail I was looking for here (search for JMP). The PC is still updated one byte at a time, I was pretty sure there was no 16-bit buffer involved; couldn't afford the silicon. The entire 6502 used only 3500 transistors. \$\endgroup\$ – tcrosley Jul 5 '15 at 11:36

Are you sure you have an 6502 in mind? From http://homepage.ntlworld.com/cyborgsystems/CS_Main/6502/6502.htm#DETAIL I get that the 6502 has a direct and indirect full-16-bit JMP.

Maybe you are thinking of a 14-bit core PIC? Fort those chips all instructions are 14-bit wide, so there is no room for enough bots to specify all address bits for the chips with larger amounts of memory, hence the address is specified in two steps: first by loading a few bits into PCH, and then by specifying the remaining bits in the jump.

But what you seem to describe is yet another thing: when, on such a PIC, you want to jump to a calculated adrress, you specify the address again in two steps, but now there are more bits in PCH that are used, and the write to PCL specifies the lower 8 bits.

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  • \$\begingroup\$ This seems to be an answer to a completely different question. \$\endgroup\$ – Dave Tweed Jul 5 '15 at 11:24
  • \$\begingroup\$ Yeah, I read the question as talking about user-accessible PCH,PCL registers. Apperanetly it is about the way the chip is implemented. \$\endgroup\$ – Wouter van Ooijen Jul 5 '15 at 11:29

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