I'm triyng to implement a 4 display counter (0 to 9999) on a Nexys 3. However, when I load the bit file, all displays remain at 0. It seems like variables a,b,c,d; which control individual digits, stay at 0, but that doesn't happen in the simulation. Xilinx throws these warnings:
WARNING:Xst:2404 - FFs/Latches <a<1:3>> (without init value) have a constant value of 0 in block <contador10000>.
WARNING:Xst:2404 - FFs/Latches <b<1:3>> (without init value) have a constant value of 0 in block <contador10000>.
WARNING:Xst:2404 - FFs/Latches <c<1:3>> (without init value) have a constant value of 0 in block <contador10000>.
WARNING:Xst:2404 - FFs/Latches <d<1:3>> (without init value) have a constant value of 0 in block <contador10000>.
WARNING:Xst:1426 - The value init of the FF/Latch a hinder the constant cleaning in the block contador10000.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch a hinder the constant cleaning in the block contador10000.
You should achieve better results by setting this init to 1.
WARNING:Xst:1710 - FF/Latch <ca_6> (without init value) has a constant value of 1 in block <contador10000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ca_2> (without init value) has a constant value of 0 in block <contador10000>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ca_1> (without init value) has a constant value of 0 in block <contador10000>. This FF/Latch will be trimmed during the optimization process.
And, if I set an initial value other than 0, it will be on the displays for a short instant before returning to 0.
I'm trying a 4 process approach:
- The clock, which generates two pulses (one for the anode switching, one for the actual count)
- A process which switches rapidly between anodes in order to display different numbers at the "same time"
- A process to asign the value of each individual digit to the established display.
- A process to do the count 0000 to 9999 and save the values in 4 digits (a,b,c,d)
This is my code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity contador10000 is
port(
clk,reset : in std_logic :='0';
led : inout std_logic := '0';
an : out std_logic_vector(0 to 3);
ca : out std_logic_vector(0 to 6)
);
end contador10000;
architecture cuenta of contador10000 is
type display is array(1 to 4) of std_logic_vector(0 to 3);
constant DISPLAYS : display := ("0111","1011","1101","1110");
type digit is array(0 to 9) of std_logic_vector(0 to 6);
constant DIGITS : digit := ("0000001","1001111","0010010","0000110","1001100","0100100","0100000","0001111","0000000","0001100");
signal i : integer RANGE 0 to 6000000 := 0;
signal j : integer RANGE 0 to 1000 := 0;
signal a,b,c,d : integer RANGE 0 to 9 := 0;
signal q : std_logic := '0';
signal x : integer RANGE 1 to 4 :=1;
begin
process(clk)
begin
if(clk'event AND clk='1') then i <= i + 1;
j <= j + 1;
if i = 6000000 then
led <= not led;
i <= 0;
end if;
if j = 1000 then
q <= not q;
j <= 0;
end if;
end if;
end process;
process(reset,led)
begin
if(reset'event and reset='1') then
a <= 0;
b <= 0;
c <= 0;
d <= 0;
else
if(led'event and led='1') then
if a = 9 then
a <= 0;
if b = 9 then
b <= 0;
if c = 9 then
c <= 0;
if d = 9 then
d <= 0;
else d <= d + 1;
end if;
else c <= c + 1;
end if;
else b <= b + 1;
end if;
else
a <= a + 1;
end if;
end if;
end if;
end process;
process(q)
begin
if q'event and q='1' then
an <= DISPLAYS(x);
if x = 4 then x <= 1;
else x <= x + 1;
end if;
end if;
end process;
process(q)
begin
if(q'event and q='1') then
case x is
when 1 => ca <= DIGITS(d);
when 2 => ca <= DIGITS(c);
when 3 => ca <= DIGITS(b);
when 4 => ca <= DIGITS(a);
end case;
end if;
end process;
end cuenta;
led
" and "q
" should probably become single strobes with all processes running on "clk
" only. Try that first and see if that makes the tools happier. \$\endgroup\$ – Aaron D. Marasco Jul 5 '15 at 23:48