The trick with this kind of question is to figure out how to use each piece of information that's given. You need to pay attention to units - for example, the cache miss penalty is given in units of ns, but all other timings are given in terms of 4 GHz clock periods. You'll have to convert one to the other in order to combine them in a meaningful way.
To start, you need to figure out how many memory references each instruction makes. We have to assume that each instruction needs one instruction fetch operation, plus we are told that 25% of instructions also make a data memory reference. That means that on the average, each instruction makes 1.25 memory references.
The cache miss rate is given as 3%, so that means that on average, each instruction is going to produce 1.25 × 0.03 = 0.0375 cache misses.
A cache miss takes 50 ns, which is 50 ns × 4 GHz = 200 clocks. Therefore, each instruction is responsible for 0.0375 × 200 = 7.5 clocks worth of cache misses.
Since each instruction takes 1.5 clocks even if there are no cache misses, the overall time is 1.5 + 7.5 = 9.0 clocks per instruction with the misses. In other words, the processor runs at only 1/6 of its peak speed when the cache miss rate is 3%.