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I want to implement a tri-state buffer for a input vector, triggered by an enable vector, where every bit of the enable vector enables the corresponding bit of the input vector.

Something like this but with multiple enable bits:

A 4 bit tri-state buffer but with a single enable bit.

A single tri-state buffer looks like this:

Y <= A when (EN = '0') else 'Z';

(example from: https://startingelectronics.org/software/VHDL-CPLD-course/tut16-tri-state-buffer/ )

It could look like this (but that one doesn't work...):

[...]
signal Y : std_logic_vector(N downto 0);
signal A : std_logic_vector(N downto 0);
signal EN : std_logic_vector(N downto 0);

Y <= A when EN = (others => '1') else (others => 'Z');

Is there a way to declare this in VHDL or do I have to write a buffer for every bit?

Edit: To clarify I'm searching a short declaration for this:

Y(0) <= A(0) when EN(0) = '1' else 'Z';
Y(1) <= A(1) when EN(1) = '1' else 'Z';
[...]
Y(N) <= A(N) when EN(N) = '1' else 'Z';
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  • 1
    \$\begingroup\$ You have to tell us what "doesn't work" means. A couple of notes: (1) EN can be a single std_logic. (2) Then Y <= A when EN = '0' else (A'range => 'Z'); ought to work. (3) Using A'range attribute instead of others makes the size of the vector explicit which will help in places where the compiler can't tell the correct range for others. \$\endgroup\$ – Brian Drummond Jul 6 '15 at 11:03
  • \$\begingroup\$ OTHERS choice used in aggregate for unconstrained record or array type is not supported that example should only demonstrate what I meant. Yes that works but it enables the complete vector. I'm searching for a compact way to describe this: Y(0) <= A(0) when EN(0) = '1' else 'Z'; Y(1) <= A(1) when EN(1) = '1' else 'Z'; [...] Y(N) <= A(N) when EN(N) = '1' else 'Z'; \$\endgroup\$ – e1kable Jul 6 '15 at 13:07
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If you need enable control for each bit, then the easiest way is to use a generate statement:

tristate : for i in 0 to N generate
begin
    Y(i) <= A(i) when EN(i) = '1' else 'Z';
end generate tristate;

Generate statements with for constraints create multiple circuits which operate in parallel, unlike a for loop in programming where the same code is executed multiple times in series.

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You have almost nailed it. Try this

signal Y : std_logic_vector(N downto 0);
signal A : std_logic_vector(N downto 0);
signal EN : std_logic;

Y <= A when EN = '1' else (others => 'Z');
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  • \$\begingroup\$ yes but here's only one enable bit. I would like to have an enable vector. \$\endgroup\$ – e1kable Jul 7 '15 at 7:27

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