I want to implement a tri-state buffer for a input vector, triggered by an enable vector, where every bit of the enable vector enables the corresponding bit of the input vector.
Something like this but with multiple enable bits:
A single tri-state buffer looks like this:
Y <= A when (EN = '0') else 'Z';
It could look like this (but that one doesn't work...):
[...] signal Y : std_logic_vector(N downto 0); signal A : std_logic_vector(N downto 0); signal EN : std_logic_vector(N downto 0); Y <= A when EN = (others => '1') else (others => 'Z');
Is there a way to declare this in VHDL or do I have to write a buffer for every bit?
Edit: To clarify I'm searching a short declaration for this:
Y(0) <= A(0) when EN(0) = '1' else 'Z'; Y(1) <= A(1) when EN(1) = '1' else 'Z'; [...] Y(N) <= A(N) when EN(N) = '1' else 'Z';