I am trying to set up a circuit with a 14.31818 MHz crystal (PAL decoding). The data sheet for the chip, using the crystal, states the relationship between the two capacitors, connecting the crystal to ground, as;

$$C_{L1} = C_{L2} = 2C_{L} -C_{STRAY}$$

I don't know what \$C_{STRAY}\$ is, neither what \$2C_{L}\$ stands for. So how do I find the two in order to calculate \$C_{L1}\$ and \$C_{L2}\$?

  • 3
    \$\begingroup\$ It would help if you could post a link to the datasheet for "the chip". \$\endgroup\$
    – stevenvh
    Aug 7, 2011 at 12:13
  • \$\begingroup\$ electronics.stackexchange.com/questions/4225/… \$\endgroup\$
    – endolith
    Aug 7, 2011 at 15:50
  • 2
    \$\begingroup\$ Your formula is wrong because of missing brackets! The correct version is: CL1=CL2=2*(CL−CSTRAY) \$\endgroup\$
    – Michael
    Nov 30, 2021 at 16:49
  • \$\begingroup\$ That frequency is four times the 3.579 MHz NTSC colour subcarrier - does it work for PAL too? \$\endgroup\$ Feb 1, 2023 at 23:36

4 Answers 4


Most likely this is a crystal intended for parallel resonant drive, and Cl is therefore the total load capacitance.

If the crystal were driven with a 0 impedance sine wave, this is the capacitance on the other side that would result in the desired phase shift at the rated frequency. Parallel resonant drive circuits rely on this phase shift to make the loop gain greater than 1 so that the circuit oscillates. This load capacitance is specified for crystals intended for parallel resonant applications. For normal crystals in the 1-25 MHz range, it's usually around 16-22 pF. For special low frequency watch crystals it is typically less, like 8-12 pF.

What the equation is trying to tell you is to split up this load capacitance equally on each side of the crystal, but to consider stray capacitance in the total. Stray capacitance is the unavoidable capacitance between nearby conductors or on the microcontroller pins to ground. It is impossible to know precisely, but 3-8 pF is a good guess, assuming reasonable layout.

While we see this very simplistic view of crystal load capacitance a lot, it is not all that good a model. This is because it ignores the output impedance of the circuit driving the signal into the crystal. At your frequency, a 18 pF capacitor would have a impedance of 620 Ω. The drive circuit can easily be substantially less than that, especially a drive circuit intended for that frequency. Think of the limiting case where the drive circuit has 0 impedance. Any capacitance added to that side of the crystal would be irrelevant.

When the drive circuit has high impedance, then the total capacitance seen by the crystal accross its leads is the series combination of the capacitance on each lead to ground. That's where the 2 in your forumula comes from. If both these capacitances are equal, then their series combination will be half of the individual values.

In summary, this equation is naive and simplistic. However, the capacitive load spec of a crystal is reasonably forgiving (one advantage of the parallel drive method), so it works well enough most of the time. If in doubt, put 22pF to ground on each side of the crystal, and it will most likely resonate nicely at very close to the rated frequency. Unless you need it to be super accurate, there is little reason to get into more detail.


\$C_{L}\$ is the load capacitance specified in your crystals datasheet. \$C_{STRAY}\$ is the stray capacitance between the two crystal traces on your board. For \$C_{STRAY}\$ I'll usually assume something in the range of 3-5 pF. But that might change depending on the length of your crystal-traces and the actual board stackup.

So, lets assume your capacitor has 20pF stated load capacitance. Then you calculate your capacitors like this. $$ C_{L1} = C_{L2} = 2 * 20pF - 5pF $$ $$ C_{L1} = C_{L2} = 35pF $$

So you might start with a 33pF or 36pF standard capacitor for a first good guesstimate. But you should measure the frequency after your first sample run and adjust the capacitors accordingly if the frequency is off.


The load capacitance is the terminal capacitance of the circuit connected to the crystal oscillator. This value is determined by the external capacitors CL1 and CL2 and the stray capacitance of the printed circuit board and connections (Cs). The CL value is specified by the crystal manufacturer. For the frequency to be accurate, the oscillator circuit has to show the same load capacitance to the crystal as the one the crystal was adjusted for. Frequency stability requires that the load capacitance be constant. The external capacitors CL1 and CL2 are used to tune the desired value of CL to reach the value specified by the crystal manufacturer.

From: https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8af-al-s-stm32-mcus-and-mpus-stmicroelectronics.pdf

And your formula is wrong. It must be...



CL is the load capacitance for the crystal you are using, it will be in the crystal specification. A value of 20 pF is quite common.

CSTRAY is the capacitance of the tracks etc. connecting the crystal to the oscillator inputs. Make it a nominal 5 pF, it won't make much difference. It could be calculated or measured, but it isn't worth the effort.


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