TL;DR: Data doesn't conclusively suggest you can do this, but it seems to be worth trying.

The data from IPC-2152 (more in the answers below) is intriguing, but doesn't seem to conclusively say that what I'm proposing is possible. However, it does say that inner layer traces aren't thermally handicapped: in fact, it seems inner layer traces have lower thermal resistance than their outer layer counterparts (at least in still air).

Let's do a quick calculation to see how this would play out, using the following parameters

  • a common 1oz/0.5oz/0.5oz/1oz 4-layer stack-up
  • 4 equally sized traces of a width that results in a 1 ohm trace resistance (large, yes, I know) for the outer layers and 2 ohms (since the copper thickness is half) on the inner layers.
  • A 10V potential across the traces


simulate this circuit – Schematic created using CircuitLab

In this case, we would see 10A on the outer layers and 5A on the inner layers. Power dissipation is then I^2R, which is 100W (10A^2 * 1 Ohm) in the outer traces and 50W (5A^2 * 2 Ohms) on the inner traces.

Given that we know the thermal conductivity of the inner traces is likely to be no worse than the outer layers, it looks like it's at least worth trying a 4-layer design, since the key worry (that the inner traces will run much hotter than the outer traces) doesn't seem to be a concern.

=================================== END EDIT

Original question:

I'm doing some high-current (40A continuous in worst case) traces on a 4-layer PCB, and I'm trying to get the space consumption down.

I've had success in the past with mirroring traces -- half of the trace goes on the top layer, and half goes on the bottom. For example, a 1" wide trace would become a 0.5" trace on the bottom and a 0.5" trace on the top.

But what about inner layers? On a 4-layer board, can I do the same across all 4 layers (e.g. 4x 0.25" traces, assuming all 4 layers are the same copper weight)?

My intuition says no -- the inner traces are much worse at shedding heat, so this may become a problem. But then again, copper has a positive temperature coefficient of resistivity, so perhaps these things balance to an equilibrium?

My question, in parts, is this:

  • Can I distribute power traces across outer and inner layers?

  • Has anyone done this and had luck/success?

  • Do the inner layer traces have to be thicker/thinner than the outer layer traces?


My response is going to be the opposite to that of @NickAleeev.

I had similar questions in the past about trace current limits and here are my findings. I haven't done real world tests to confirm this (yet).

The standard for current capacity in a trace was established in a document (IPC-2221) which is what alot of online calculators use. The document is old and outdated. The new standard is the IPC-2152. The IPC-2221 is conservative, and if you can go that route it might be best too. If however, you are limited in space, then IPC-2152 would give you better results. Different calculators will give you different answers, depending on what standard they are basing it off. I have only found two calculators that use IPC-2152 and when I asked my fab house, they said that they can't tell me.

Also internal layers while they are sandwiched (in FR4) have a greater thermal conductivity than air. (The link below goes a bit more into it). They will dissipate the heat more to the surface, and if you have a solid plane between your internal layer and the outer layer, you have a pretty good sink for all that heat.

Have a look at a question I had asked in the past [what is the current limit through a trace? ] you can probably just jump to the end of the question and read the answer.

Some advice I got from this, was just build a dummy board, inject your current into a trace, and see how it reacts. All the, this table says this, that table says that, can't beat an experiment that you can test yourself.

  • \$\begingroup\$ I would say that on balance what you wrote tells me that multi-layer power-carrying traces are at least worth trying, and likely possible. It would be nice to be able to mark both answers with the green check-mark, since I needed both to come to a conclusion. \$\endgroup\$ – PKL Jul 7 '15 at 19:07

[ disclaimer: I haven't done parallelization of traces into inner layers. I'm speaking only from general sense. ]

Yes, you can parallelize traces into inner layers.

Yes, the traces on inner layers are worse at dissipating heat. If you want to split the current evenly, the inner traces should be wider than the surface traces. The calculation in the IPC standard accounts for that. If you look at the trace width calculator, you'll notice that it produces larger trace widths for inner than outer.

Remotely related article in PCD&F: Trace Current/Temperature Relationships. Thermal simulation plots.

  • \$\begingroup\$ Nick, your link and @efox29's data both suggest that traces on inner layers dissipate heat better because air is a worse thermal conductor than the board substrate. The quote is: IPC-2152 also provides data for internal traces and traces in a vacuum. Perhaps the most surprising result in the standard is that internal traces actually run cooler than do external traces! This is a major change from the previous standard. The traces run cooler because the dielectric materials conduct heat away from the trace better than does the air. \$\endgroup\$ – PKL Jul 7 '15 at 18:46

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