fpga clock muxing

Question

We are using an fpga with limited resources, the IGLOO Nano, so to implement all our functionality, we need to share a FIFO between two different vhdl components, which are using different clocks.
The functionality is as shown below:

DATA(SCLK) -->|------|              |----------|
              | MUX  |------------->|DATA      |
DATA (CLK) -->|------|              |          |
                                    |   FIFO   |
    SCLK ---->|------|              |          |
              | MUX  |------------->|WCLK      |
    CLK  ---->|------|              |----------|

SCLK=27MHz and CLK=13.5MHz are not related.
DATA is either synchronous with the SCLK or CLK, depending on which is selected in the MUX.
The synthesizer tool shows a warning: While analyzing gated clock network, ambiguities have been found on gates
My problem is that DATA is not clocked correctly into the FIFO, and the post place and route simulation confirms this. The DATA is not correctly aligned with WCLK, when arriving at the FIFO input port.
How do I constrain a design like shown above, so data is always synchronous with the WCLK ?
EDIT: additional information, the MUX select pin does not change often.

Answer 1

I would discourage you from trying to MUX the clocks like you show. You are already seeing that there are issues of trying to use gated clocks.

My suggestions -

1. Find a larger FPGA that is not so resource constrained for your design. There are a lot of good choices out there that are economical.

2. Find a way to combine your clock domains into one so that one common clock can drive the whole design.

3. Partition your design to be in two separate devices with each device supporting a single clock domain.