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We are using an fpga with limited resources, the IGLOO Nano, so to implement all our functionality, we need to share a FIFO between two different vhdl components, which are using different clocks.
The functionality is as shown below:

DATA(SCLK) -->|------|              |----------|
              | MUX  |------------->|DATA      |
DATA (CLK) -->|------|              |          |
                                    |   FIFO   |
    SCLK ---->|------|              |          |
              | MUX  |------------->|WCLK      |
    CLK  ---->|------|              |----------|

SCLK=27MHz and CLK=13.5MHz are not related.
DATA is either synchronous with the SCLK or CLK, depending on which is selected in the MUX.
The synthesizer tool shows a warning: While analyzing gated clock network, ambiguities have been found on gates
My problem is that DATA is not clocked correctly into the FIFO, and the post place and route simulation confirms this. The DATA is not correctly aligned with WCLK, when arriving at the FIFO input port.
How do I constrain a design like shown above, so data is always synchronous with the WCLK ?
EDIT: additional information, the MUX select pin does not change often.

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  • \$\begingroup\$ Since CLK is exactly half the rate of SCLK, is there a way to make them related? It seems that doing this would make the scenario much simpler, as you could then implement all the logic using SCLK with an enable signal. \$\endgroup\$ – scary_jeff Jul 9 '15 at 8:26
  • \$\begingroup\$ Unfortunately the SCLK and CLK are from different clock domains, so the frequency is not exactly either. \$\endgroup\$ – JakobJ Jul 9 '15 at 8:36
  • \$\begingroup\$ I guess what I'm getting at is whether it would be possible to alter the circuit so that one of these two clocks really was exactly double the rate of the other. \$\endgroup\$ – scary_jeff Jul 9 '15 at 8:39
  • \$\begingroup\$ I'm not familliar with the Microsemi devices, but if I had to do this on say a small Spartan-6 FPGA then I would try manually instanciating a clock mux and buffer primitive (BUFGMUX). Other solutions are probably better though. \$\endgroup\$ – Xcodo Jul 9 '15 at 15:18
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    \$\begingroup\$ How is your data coming from one of two different clock domains? Do you have another MUX that selects between two different sets of output registers? Or is this coming components external to the FPGA? \$\endgroup\$ – alex.forencich Jul 9 '15 at 17:05
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I would discourage you from trying to MUX the clocks like you show. You are already seeing that there are issues of trying to use gated clocks.

My suggestions -

  1. Find a larger FPGA that is not so resource constrained for your design. There are a lot of good choices out there that are economical.

  2. Find a way to combine your clock domains into one so that one common clock can drive the whole design.

  3. Partition your design to be in two separate devices with each device supporting a single clock domain.

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