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In my application, I am using LPC2138 controller and TI's TLV320DAC3100 DAC with built in amplifier to interface audio data.

To implement I2S interface using SPI, some extra hardware circuitry needed which I found from below link:

http://www.ti.com/lit/an/slaa449a/slaa449a.pdf

From above application note, I am able to get following hardware for SPI - I2S interface.

SPI to I2S conversion

And 5 bit counter is implemented as follows:

SPI to I2S circuit

My question is above note is specifically for MSP430F Texas controller and I need to interface with NXP LPC2138 controller.

In that case,Is this design logically correct for interfacing I2S on SPI bus? Or LPC associated hardware will differ for such implementation.

Thank you.

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    \$\begingroup\$ If it works for SPI on MSP430 then definitely yes for LPC. thanks for the nice question \$\endgroup\$ – Umar Jul 9 '15 at 10:50
  • \$\begingroup\$ @Umar Thanks I am referring TI application note ti.com/lit/an/slaa449a/slaa449a.pdf \$\endgroup\$ – Electroholic Jul 9 '15 at 10:51
  • \$\begingroup\$ If anyone is trying to use a Kinetis microcontroller (from NXP, formerly Freescale) and trying to do the same trick, they have their own whitepaper: "Emulating I2S bus on Kinetis-M" cache.freescale.com/files/microcontrollers/doc/app_note/… I am interested in doing this on their MK02 line of chips, because they are very cheap and run very fast (up to 100mhz). \$\endgroup\$ – drojf Jan 26 '16 at 7:22
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Oh, be careful with the NXP SPI controllers. I can only tell from experience with the LPC1768 but it seems that at least one of the two SPI peripherals are identical.

As said, there are two SPI controllers in your chip. I can't tell much about the first one (the ordinary SPI controller without FIFO). It may just work for your task, but - no FIFO, so very high CPU load.

The second one, called SPI1/SSP, is tricky because it demands that the chip-select line goes high between each transfer word for at least one clock cycle. This makes it impossible to transfer a continuous bit-stream without gaps. You will not be able to directly interface I2S in SPI mode.

You can however configure the SPI1/SSP in TI SSI mode. In this mode the chip-select line becomes a frame syncronization signal that stays low most of the time but pulses high on each least significant bit. The transfer will be continuous without single bit gaps so it interfaces nicely with your I2C codec.

You may be able to derive the I2S Word-Select signal from this using a single divider flip-flop. Deriving directly from clock like you suggested would work just as well.

I suggest that you take a look at figure 26 in the user manual UM10120:

TI-SSI Mode

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  • \$\begingroup\$ You are talking about SCK0 MOSI0 MISO0 SSEL0 pins, which will work fine? \$\endgroup\$ – Electroholic Jul 9 '15 at 11:36
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    \$\begingroup\$ The pins you've mentioned are for the SPI peripheral, not the SPI1/SSP peripheral that needs to be run in TI SSI mode. So yes, it will likely work. You won't have a FIFO for the simple SPI peripheral, that means that you have to constantly read and write data. e.g. you'll have a very high CPU load. \$\endgroup\$ – Nils Pipenbrinck Jul 9 '15 at 11:41
  • \$\begingroup\$ SSP is simply the name of the more advanced SPI peripheral. It does not only do standard SPI but some common variations of SPI like TI SSI as well. It's more flexible and powerful than the SPI you're currently using. And it has a FIFO :-) \$\endgroup\$ – Nils Pipenbrinck Jul 9 '15 at 11:53
  • \$\begingroup\$ So I can use SSP rather using SPI. Overhead on controller will reduced since it has FIFO? \$\endgroup\$ – Electroholic Jul 9 '15 at 12:02
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    \$\begingroup\$ @Electroholic Yes. In the long run you'll be much happier using the SSP in TI-SSI mode. \$\endgroup\$ – Nils Pipenbrinck Jul 9 '15 at 12:08

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