DRAM is built as a capacitor and a switch for each bit - the data is stored as a charge on the capacitor.
It is pretty much impossible to make a perfect capacitor and a perfect transistor, certainly not on the tiny scale used in DRAM chips. There are leakage currents within the system - between the capacitor plates, across the channel of the transistor, etc.
This means that the charge stored on the capacitor will, over time, discharge. As the charge dissipates, the voltage on the plates gets smaller and smaller until it is indistinguishable whether it is a 1 or a 0 - it ends up being somewhere in between. At this point the data is lost or at the very least corrupted.
In practice, the way this is avoided is to periodically read every data bit in the RAM and then write the same value back. What this does is rebuild the charge on the capacitor to replace any that has leaked away. This process is called refreshing. If you turn the power off, the controller that is periodically refreshing the DRAM turns off and so it is no longer restoring the charge on each bit and the data eventually seeps away.
Furthermore, during operation when you access a bit in the DDR, the capacitor discharges a little bit through the access transistor - as the charge on the capacitor is shared with the capacitance of the access lines. So in order for the bit to not change, you have to write the same value back to restore the charge in the capacitor.