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Let me clarify, we all know Dynamic RAM is volatile in nature (it just won't hold data when it's turned off).

I've been searching throughly about why instead of the 'what' about it, I just can't find a technical reason about why it won't hold permanent data.

I would like to know 'why' it doesn't hold permanent data (technically).

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    \$\begingroup\$ Typing DRAM into Google gave plenty of references. Question should be closed - insufficient research. \$\endgroup\$ – Leon Heller Jul 11 '15 at 13:06
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    \$\begingroup\$ What might be informative would be to compare the structure of a DRAM cell to that of an EPROM cell. Both are about storing charge, but in the former the duration of useful storage is measured in milliseconds and in the later years. \$\endgroup\$ – Chris Stratton Jul 11 '15 at 16:37
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    \$\begingroup\$ @LeonHeller It seems like you are unfamiliar with how this site works. Perhaps you should stop saying that every question should be closed? \$\endgroup\$ – W5VO Jul 12 '15 at 0:06
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DRAM is built as a capacitor and a switch for each bit - the data is stored as a charge on the capacitor.

It is pretty much impossible to make a perfect capacitor and a perfect transistor, certainly not on the tiny scale used in DRAM chips. There are leakage currents within the system - between the capacitor plates, across the channel of the transistor, etc.

This means that the charge stored on the capacitor will, over time, discharge. As the charge dissipates, the voltage on the plates gets smaller and smaller until it is indistinguishable whether it is a 1 or a 0 - it ends up being somewhere in between. At this point the data is lost or at the very least corrupted.

In practice, the way this is avoided is to periodically read every data bit in the RAM and then write the same value back. What this does is rebuild the charge on the capacitor to replace any that has leaked away. This process is called refreshing. If you turn the power off, the controller that is periodically refreshing the DRAM turns off and so it is no longer restoring the charge on each bit and the data eventually seeps away.

Furthermore, during operation when you access a bit in the DDR, the capacitor discharges a little bit through the access transistor - as the charge on the capacitor is shared with the capacitance of the access lines. So in order for the bit to not change, you have to write the same value back to restore the charge in the capacitor.

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  • \$\begingroup\$ Note that the floating gate of an EPROM cell's transistor does orders of magnitude better at retaining charge - suggesting that it's not that building something which will do so is difficult, but rather that it has consequences such as a longer and higher voltage write process (and then there's erasure - both issues that have been juggled in different ways in subsequent non-volatile technologies) \$\endgroup\$ – Chris Stratton Jul 11 '15 at 16:40
  • \$\begingroup\$ @ChrisStratton it's really a different issue - in (E)EPROM, the gate is storing a charge, so the leakage is from gate to channel (and/or substrate) which is generally easier to make quite small. With DRAM the leakage is within the capacitor itself (from plate to plate and substrate), and through the channel of the transistor. With DRAM also due to the density requirement of modern chips, the transistors are much smaller meaning thinner oxide layers, shorter channels and lower threshold voltages which means higher leakage. \$\endgroup\$ – Tom Carpenter Jul 11 '15 at 17:05
  • \$\begingroup\$ What the EPROM cell demonstrates is that it is possible to store charge for years, which is what the DRAM capacitor fails to do (if you want to argue that the leakage is in the capacitor itself, vs. its access mechanism). In terms of size, remember that its modern descendants are (at least volumetrically) quite a bit denser than DRAM (or at least the access wiring required for random access). Rather, what seems to be at issue is that the cost of such insulation is greater difficulty of and hence time for (re)writing. \$\endgroup\$ – Chris Stratton Jul 11 '15 at 17:15
  • \$\begingroup\$ @ChrisStratton I see your point. I suppose the difference is that the capacitor used for DRAM has to be much larger than the gate used for Flash/(E)EPROM because of the access requirements of the technology - when you access a DRAM bit, the charge on the capacitor is shared with the capacitance of the bit line, so you have to make it large enough to drive that line. The trouble with that is in making it larger rather than being able to surround it by a nice thick oxide layer like you would a floating gate, you have to build down into the substrate which results in higher leakage. \$\endgroup\$ – Tom Carpenter Jul 11 '15 at 17:36
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Nearly all forms of computer memory store information in the form of electrical charges, or to be more precise, the patterns in which electrons are distributed. Storing information generally entails allowing electrons to move to the places where they're supposed to be and away from those they aren't; holding information entails making it difficult for electrons to move where they shouldn't, if some do, using an external source of energy to repopulate the places that should have electrons and re-empty the places that shouldn't.

As a general rule, it's easy to make something that can switch between offering extremely low resistance and moderately high resistance to electron flow, or that can switch between moderately low resistance and extremely high resistance, but it's often not practical to switch between extremely low and extremely high resistance. The more quickly electrons are able to flow into the places they're supposed to within a RAM, the less effectively they'll be held there. Memory technologies like flash make it very difficult for electrons to flow where they're not supposed to, but on the flip side they also make it much harder to get the electrons where they need to be in the first place.

Incidentally, static RAM chips have a circuit for each memory cell to continuously charge or empty it as necessary for it to keep its state; in a DRAM chip, the circuity responsible for charging/emptying any given cell will also be shared with thousands of others. Having this circuitry shared between some cells which hold ones and some which hold zeros means that it will have to repeatedly switch between charging and charging memory cells; all that switching takes energy. Static RAM lets each piece of circuitry remain in charging or discharging mode without wasting any energy switching modes.

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Drams store their bits on capacitors and there are transistors that connect to select each of these caps for reading and writing by the sense amplifiers. Even the best transistors have leakage which means the capacitors will slowly discharge over time. This is also why drams have a requirement for refresh cycles.

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I think these other two answers, while they address the mechanism of dynamic RAM (DRAM), don't completely address the issue of volatile vs non-volatile memory.

As the other answers have described, it is necessary to periodically refresh DRAM to keeps its contents from fading away. The opposite to this is static RAM (SRAM), which does not needed refreshing.

Why not use SRAM all the time? Because it uses a lot more circuitry -- six transistors per SRAM cell vs the transistor and capacitor for a DRAM cell.

The kicker is both of these types of RAM are volatile, i.e. they will lose their contents when power is removed. Whether a memory is volatile or not when the power is turned off doesn't matter whether it is SRAM or DRAM. So I think the emphasis on DRAM is misdirected (I know it was mentioned in the question, but I'm trying to point out that RAM is the issue, not a specific type of RAM.)

Non-volatile memory are those types that don't lose their contents when power is removed, such as flash, ROM (read-only memory), and EEPROM (electrically eraseble programamble ROM), among others.

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  • \$\begingroup\$ 'RAM' isn't always the issue. FeRAM (FRAM) has the same random access capabilities as SRAM, but is in fact non-volatile, as is PRAM (Phase-Change RAM). The question itself was about what property of DRAM is it that makes it volatile. \$\endgroup\$ – Tom Carpenter Jul 11 '15 at 15:54
  • \$\begingroup\$ @TomCarpenter Re RAM, I was referring to mainstream technologies, there will always be some exceptions. This Wikipedia article says "Most general purpose Random Access Memory (RAM) is volatile". Re what property of DRAM is it that makes it volatile, its that it loses its contents when power is turned off, same as SRAM. That's what volatile memory means (see same article cited earlier). Has nothing specifically to do with refresh.. \$\endgroup\$ – tcrosley Jul 11 '15 at 17:56
  • \$\begingroup\$ We are in complete agreement about the meaning of volatile memory - my understanding of the question was what part of the technology itself results in the loss of data when powered off. Interesting PRAM is starting to come into the mainstream - there is at least one Samsung phone which uses it for memory, I did a review on the technology as part of one of my Uni modules, it's quite interesting stuff in how it works. \$\endgroup\$ – Tom Carpenter Jul 11 '15 at 18:08

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