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I have used non volatile memory, like EEPROM and FLASH memory, in embedded applications and I have always found that unused memory (EEPROM/FLASH) bit locations are always set to 1 by default. Why is this used instead of 0?

For example an address, say 0th address (first byte of memory), if not written to by the user, always stores 0xff and not 0x00. Why is it that people who built the memory chips kept it that way? I'm sure keeping the default memory location as 0xff would provide some advantage or something important for the manufacturer.

What is the reason behind this structure in memory chips?

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I am going to discuss flash memory programming, but a lot of material will be similar to EEPROMs (Electrically Erasable Programmable ROM), since flash memory was derived from EEPROMs in the mid 1980's. As described below, from a physical standpoint, the default state is 1's. But more importantly, I'm going to explain why there is a default state -- you can't just arbitrarily program on top of what is already programmed from last time.

NOR flash is almost always chosen for program flash since the interface is best suited for placing the data within the memory map of the microcontroller -- full address and data busses mimic RAM and allow random access to any location. Data can be read one word at a time, where a word is defined as the data width of the microcontroller, typically 8, 16, or 32-bits. NAND flash, on the other hand was developed to replace hard drives and works sequentially.

However programming gets a little more complicated. As already mentioned, the default state for NOR flash and other non-volatile memories like NAND flash, EEPROMs and even EPROMs is a logic 1. You cannot program 1's into these devices, you can only program 0's. So for example if you have a byte containing 0x0123 and you want to change it to 0x3210, you can't do so directly like writing over a byte in RAM.

Instead, bits in the memory must be erased, which puts them into the default 1 state already mentioned. This can only be done in blocks, not words. On the Microchip PIC32, which I have worked with the most lately, the minimum block size that can be erased is 4096 bytes. So if you wanted to change just one word (32-bits), you would have to read the 4K of memory, erase the block, then write the 4K of memory back to flash but including the new 32-bit value as needed. This erasing can take some time -- a good part of a second.

The following is a picture of a flash memory cell. Flash stores the data by removing or putting electrons on the floating gate. When electrons are present on the floating gate, no current flows through the transistor, indicating a 0. When electrons are removed from the floating gate, the transistor starts conducting, indicating a 1. (This is by convention -- it could have been the other way but would required inverters on all the data lines.)

enter image description here

Erase operation. The default state of flash memory cells (a single-level NOR flash cell) is 1 because floating gates carry no negative charges. Erasing a flash-memory cell (resetting to a 1) is achieved by applying a voltage across the source and control gate (word line). The voltage can be in the range of -9V to -12V. And also apply around 6V to the source. The electrons in the floating gate are pulled off and transferred to the source by quantum tunneling. In other words, electrons tunnel from the floating gate to the source and substrate.

Because erasing uses high voltages, so erasing in blocks requires less die area. So voltages can only be applied to entire rows of transistors at a time.

For writing, a NOR flash cell can be programmed, or set to a 0 by the following procedure. While writing, a high voltage of around 12V is applied to the control gate (word line). If a high voltage around 7V is applied to bit Line (drain terminal), a 0 is stored in the cell. The channel is now turned on, so electrons can flow from the source to the drain. The source-drain current is sufficiently high to cause some high-energy electrons to jump through the insulating layer onto the floating gate via a process called hot-electron injection.

For reading, a voltage of around 5V is applied to the control gate and around 1V to the drain. The state of the memory cell is distinguished by the current flowing between the drain and the source.

The useable life of non-volatile memory is measured in terms of erase cycles. The disadvantage of NOR is that the number of erase cycles is about 1/10 that of NAND memory. Many versions of the PIC32 only allow the flash memory to be updated 1000 times, way less then the typical 100,000 erase cycles for EEPROMs.

So it is not so important if the designers made the default state is 1 or 0 (they chose the value that permitted the easiest implementation); the important thing is that one has to erase a block of flash first (which takes time), and then reprogram the entire block (even if a single word is being changed (which requires a substantial amount of RAM).

This block erasing of the device goes back to the first EPROMs (Erasable Programmable ROM), which proceeded EEPROMs The code was programmed into chips (like the 16KB 27128) and placed in sockets. These chips had a little window on top which allowed light to shine on the die. When the program had to be changed, the chips were put into a UV eraser for 20 minutes or so, which would erase the entire chip. Then the chip would be programmed with the new program.

Some EEPROMs require erasing of blocks of memory before programming; others allow writing a byte at a time (the EEPROM controller actually erases the byte first and the programs it).

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    \$\begingroup\$ This is a great overview of how nonvolatile memories are accessed, but it doesn't actually address WHY the erased state is '1' and not '0'. \$\endgroup\$
    – akohlsmith
    Jul 12, 2015 at 19:47
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    \$\begingroup\$ @akohlsmith I added that information to be more complete. But the real issue not whether the default cell is a 1 or a 0; this could be reversed just by putting inverters on each data line. The real issue is why there is a default state in the first place; i.e. you can write a 0 by not a 1 -- the latter requires erasing in blocks. \$\endgroup\$
    – tcrosley
    Jul 12, 2015 at 23:30
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    \$\begingroup\$ I disagree, the question seemed quite specific about why the erased state is 'set' rather than 'clear' -- anyway I love your answer, and +1 from me (not that I'm anyone, just a random internet stranger who likes your answer) \$\endgroup\$
    – akohlsmith
    Jul 13, 2015 at 0:36
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    \$\begingroup\$ @akohlsmith I agree with you that by convention, set states are usually 1, and that in fact is how the individual cells work. It would take some extra hardware (not much) to reverse it, and there was no need to do so: 1 as the default was just fine. \$\endgroup\$
    – tcrosley
    Jul 13, 2015 at 1:14
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    \$\begingroup\$ This is a great answer. But I think it will be easier to understand if say: you cannot program 1's into these devices, you can only program 0's. If you want to program 1's, you have to erase the devices and restore the whole block back to the default 1 state, and then program 0's as necessary.. For example, to program 0101 to 1010, you have to do in this sequence: 0101 ->(erase)->1111->(program 0's)->1010. Or essentially, it means the write of 1 and write of 0 are done at different granularity. \$\endgroup\$ Sep 17, 2018 at 5:34
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In modern flash memory, I don't know of any reason to choose ones over zeros as the default. Reads are done via differential current sense amplifiers, so in principle you could take the output from either side. (The first EEPROMs might have had simpler read circuits -- I'm not sure.)

There is a good reason not to add extra inverters -- it would increase the propagation delay from the memory to the CPU. In microcontrollers, the flash to CPU datapath has a huge effect on overall system performance, since it determines how long it takes to fetch new instructions.

Digital circuit designers often expect zero to mean clear/reset/erased. But flash transistors and read circuitry are analog. From that standpoint, describing the conducting state of the flash transistor as a logical one makes more sense. And it just so happens that going from a one to a zero is much, much faster than going from a zero to a one, so one becomes the "erased" state while zero becomes the "programmed" state.

Short version: Semiconductor physicists and analog circuit designers care nothing for your digital intuitions. :-)

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I'm not sure what it is you're quoting from, but going off the Wikipedia page for flash memory, it seems to be a result of the hardware behind flash memory:

A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down."

If you were to use another type of flash, e.g. NAND, the default state would be 1 because the output of NAND is 1 when any of the transistors' output is below their high/low threshold voltage.

Apologies if I totally missed the boat on what you were asking, I'm fairly new to all of this as well.

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    \$\begingroup\$ But given that there is circuitry between the cells and the pins, that like most logic constructs probably inherently performs a number of implicit inversions, why is the erased state necessarily used as a "0" and not as a "1" ? \$\endgroup\$ Jul 12, 2015 at 21:35
  • \$\begingroup\$ I don't quite understand your question--is the ERASE state not used as "1"? I ask with respect to this (under "EEPROM MEMORY CELL OPERATION AND CHARACTERISTICS"). \$\endgroup\$
    – llee94
    Jul 12, 2015 at 22:30
  • \$\begingroup\$ Which electrical state of the cell itself corresponds to which logical state of the external interface seems nearly arbitrary, as there are multiple, probably implicity inverting circuit elements between the two. \$\endgroup\$ Jul 12, 2015 at 23:05
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    \$\begingroup\$ @ChrisStratton I believe Ilee94 said the erased state is actually a 1. But it is actually arbitrary - if you put inverters on the data lines it would be as you described. 1 as the default state simply requires a little less hardware. \$\endgroup\$
    – tcrosley
    Jul 12, 2015 at 23:43
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    \$\begingroup\$ Or a little more hardware - it really depends of if there's an odd or even number of implicitly inverting circuit elements between the cell and the output. \$\endgroup\$ Jul 13, 2015 at 0:57
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The ROMs and PROMs of way back when had to be manipulated by adding metal in the mask layer during manufacture or burning it away in programming and both processes had a default high state when manufactured. Having them default to LOW would have cost more transistors, reduced the programming convenience or operating speed in some way.

It has since become convention because adding an inverter at some point in the data path these days would be possible.

The convention may have started in the days of diode logic memory arrays that had diodes to pull down data lines when they were addressed and unused memory words would have no diodes instead of all the diodes. Most early digital logic standards were actively pulled LOW and floated high if not.

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