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It appears that most FPGA boards, such as the Mojo and Papilio, have built-in clocks on the order of 50 MHz, even though the FPGA chips themselves can go up to several hundred MHz. However, I need to be able to control another device with a signal on the order of 150 MHz. Are there FPGA boards that might be suitable?

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PLL - you feed a low frequency clock in, you get a high frequency clock out.

Even with PCIe Gen3 as an example this is how it's done - you use a 100MHz reference clock and use a PLL to increase it to 4GHz.

So really any board which has I/O buffers capable of the frequency you require (150MHz) and a clock that is of a nice multiple of it (50MHz could be multiplied easily by 3), then the board electrically should work for your application - as long as whatever connections on your development kit are suitable (e.g. length matched if needed). Without knowing more about the specific application/device you want to control or even the dev board you are using it is hard to say what is suitable.

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You do not necessarily need another FPGA board for this purpose. Most FPGAs have clock multipliers as primitives (for example, Xilinx FPGAs having DCMs and other tools that allow multiplying and dividing clocks, and Altera having PLL modules). You can configure these primitives to multiply your input clock to the speed you need (even non-integer multiples, at least on Xilinx DCM_SPs)

Remember that on a development board, signal line routing may not be optimal for all pins, especially if they're going to a lower-frequency connector such as header pins, or a solderless breadboard that is mounted on some FPGA devboards (more common in educational settings)

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  • \$\begingroup\$ Since when does Xilinx offer CPUs? \$\endgroup\$ – Paebbels Jul 13 '15 at 5:51
  • \$\begingroup\$ @Paebbels I think hexafraction ment FPGAS, not CPUs. Xilinx has combo-chips with FPGA fabric and CPUs these days though. Take a look at their Zynq line of chips. \$\endgroup\$ – Nils Pipenbrinck Jul 13 '15 at 8:07
  • \$\begingroup\$ @paebbels that was just a typo. \$\endgroup\$ – Andrey Akhmetov Jul 13 '15 at 11:52
  • \$\begingroup\$ @Paebbels ... since the Virtex-II Pro. Which was quite a long time ago... \$\endgroup\$ – Brian Drummond Jul 13 '15 at 12:59
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The highest external reference clock I know of is 200 MHz with differential signaling.

There are 2 ways to increase this frequency:

  1. As descibed by Tom you can use a Clock Modifying Block (CMB) in the FPGA like PLL, DCM or MMCM to generate a high frequency clock that is a multiple of your reference clock.

  2. Some FPGA boards are shipped with programmable oscillators. E.g. the Si570 can be programmed from 1 to 910 MHz. But most boards have not so good routing and material for such high frequencies.

Keep in mind: Internal CMBs have a bad jitter performance compared to external dedicated clock/oscillator chips.

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