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I have been learning about the AVR sleep modes as I would like to start using them in my future projects. I think I have understood the most of it except some specific details below

  1. Under Power Reduction Register (PRR), it mentions that using this to turn off the clock to a peripheral freezes the peripheral in it's current state with the I/O registers becoming inaccessible. Also the resources used by this peripheral would remain unoccupied. So its suggested to disable to peripheral before stopping the clock to it.

  2. Under AVR-gcc documention of , they have provided the atomic instructions (sleep_enable, sleep_cpu and sleep_disable) besides the all automatic sleep_mode macro. The reason given is that sleep_mode might case race condition in some cases.

Can someone please explain the above 2 points in more detail.

Thanks!

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  • \$\begingroup\$ Which part? The first should be mostly self-explanatory, except for the typo you added, and the second should be obvious, since there are multiple steps required in order to put a device to sleep. \$\endgroup\$ – Ignacio Vazquez-Abrams Jul 13 '15 at 8:12
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  1. When you disable a peripheral, you can turn it on with one instruction and resume it - meanwhile all resources used by this particular peripheral are freed and you are free to use them. When you turn the clock off you put the peripheral to wait - its resources can't be freed, since it requires a clock pulse to execute clearing instruction. Only thing you could do is turn the clock signal back on and resume using it.

  2. Race condition mentioned concerns pipeline stages in your CPU. To keep things short - your CPU processes more than a one instruction, and using correct variable values is based on when the instruction was fetched and decoded. If you modify one register/variable/bitfield sequentially with different instructions, there is a chance, that one of the instructions in given sequence would fetch a value before its processed by previous instructions, changing the output of operation, and therefore state of the circuit as a whole.

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  • \$\begingroup\$ Are you sure? I thought they had two stage pipeline - when one instruction is executed, another one is pre-fetched from memory. \$\endgroup\$ – Sven Jul 13 '15 at 9:10
  • \$\begingroup\$ Oh, you're correct, they do. \$\endgroup\$ – Ignacio Vazquez-Abrams Jul 13 '15 at 9:12

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